Alternatives and similar repositories for hlsclt

Users that are interested in hlsclt are comparing it to the libraries listed below

• sgherbst / svreal
  Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
  ☆45Updated 4 years ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆70Updated 9 months ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆62Updated 2 years ago
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆55Updated 3 weeks ago
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• PyHDI / ipgen
  IP-core package generator for AXI4/Avalon
  ☆22Updated 6 years ago
• chipsalliance / python-fpga-interchange
  Python interface to FPGA interchange format
  ☆41Updated 2 years ago
• slaclab / ruckus
  FPGA and Digital ASIC Build System
  ☆74Updated last week
• antmicro / cocotb-verilator-build
  ☆26Updated last year
• Nic30 / hwtLib
  hardware library for hwt (= ipcore repo)
  ☆39Updated last week
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆57Updated 8 months ago
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆78Updated 4 years ago
• maltanar / rosetta
  Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ
  ☆33Updated 6 years ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆27Updated 3 years ago
• dirjud / Nitro-Parts-lib-Xilinx
  This is mainly a simulation library of xilinx primitives that are verilator compatible.
  ☆33Updated 11 months ago
• chipsalliance / fpga-interchange-schema
  ☆56Updated 2 years ago
• unihd-cag / openhmc
  openHMC - an open source Hybrid Memory Cube Controller
  ☆49Updated 9 years ago
• FPGA-Research / zynq-ultrascale-readback-capture
  This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…
  ☆16Updated 5 years ago
• hgomersall / Ovenbird
  A tool for merging the MyHDL workflow with Vivado
  ☆20Updated 5 years ago
• chipsalliance / UHDM-integration-tests
  ☆31Updated last year
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆42Updated 2 years ago
• verilator / example-systemverilog
  ☆39Updated last year
• maltevesper / JetStream-hardware
  ☆22Updated 8 years ago
• umarcor / osvb
  Open Source Verification Bundle for VHDL and System Verilog
  ☆45Updated last year
• csail-csg / pyverilator
  Python wrapper for verilator model
  ☆86Updated last year
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆51Updated 3 years ago
• greenblat / vlsistuff
  ideas and eda software for vlsi design
  ☆50Updated this week
• SymbioticEDA / sva-demos
  SVA examples and demonstration
  ☆16Updated 4 years ago
• Inkub / SV-assertions-IF-generator
  Generates a SystemVerilog assertion interface for a given SV RTL design
  ☆18Updated 3 months ago
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆42Updated last year