Verilator Porcelain
☆48Nov 7, 2023Updated 2 years ago
Alternatives and similar repositories for verilated-rs
Users that are interested in verilated-rs are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 🦀 No-nonsense hardware testing/simulation in Rust 🛠️ | Verilog, Spade, Veryl☆126Oct 3, 2026Updated 2 weeks ago
- Minimal RISC-V RV32I CPU design as described in a companion blog post.☆13Jun 14, 2020Updated 6 years ago
- egraph on top of sqlite☆13Mar 8, 2022Updated 4 years ago
- A Coq framework to support structural design and proof of hardware cache-coherence protocols☆15May 7, 2022Updated 4 years ago
- A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.☆19Jul 7, 2022Updated 4 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Examples for creating AXI-interfaced peripherals in Chisel☆76Nov 15, 2015Updated 10 years ago
- FPGA synthesis tool powered by equality saturation and program synthesis.☆15Jan 9, 2026Updated 9 months ago
- Verilog AST☆19Dec 2, 2023Updated 2 years ago
- ☆45Sep 1, 2026Updated last month
- IA-64 emulator☆15Aug 13, 2021Updated 5 years ago
- Rust bindings for CIRCT☆19Apr 20, 2024Updated 2 years ago
- ☆11Dec 18, 2017Updated 8 years ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆96Aug 10, 2018Updated 8 years ago
- LLVM JIT Cycle Accurate Simulator for HardCaml☆13May 21, 2017Updated 9 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- ☆12May 20, 2021Updated 5 years ago
- Experiments with Yosys cxxrtl backend☆49Jan 16, 2025Updated last year
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆482Jun 10, 2026Updated 4 months ago
- A 6800 CPU written in nMigen☆49Jun 16, 2021Updated 5 years ago
- Easy SMT solver interaction☆36Feb 3, 2026Updated 8 months ago
- RISC-V 64 CPU☆10Oct 4, 2025Updated last year
- ☆16Jan 25, 2026Updated 8 months ago
- ☆28Dec 4, 2025Updated 10 months ago
- A simple digital waveform viewer with vi-like key bindings.☆145Mar 7, 2025Updated last year
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Chisel Fixed-Point Arithmetic Library☆18Dec 15, 2025Updated 10 months ago
- I want to learn [n]Migen.☆44Jan 26, 2020Updated 6 years ago
- ☆23Updated this week
- batch eval tool for machine code. eval() but for asm.☆12Dec 31, 2022Updated 3 years ago
- ☆11Nov 21, 2021Updated 4 years ago
- Small Stack-Based Computer Compiler -- Verilog micro controller for FPGA housekeeping with peripherals☆16Jan 11, 2020Updated 6 years ago
- a toolset for autogenerating rust APIs and translating structs☆25May 30, 2018Updated 8 years ago
- Locus site for Public Review of Several RISC-V ISA Formal Specs☆76Jun 18, 2020Updated 6 years ago
- Whisk: 16-bit serial processor for TT02☆13Sep 30, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- CPU敏捷开发框架（龙芯杯2024）☆28Sep 6, 2024Updated 2 years ago
- A language for symbolic transitions system, inspired by Ivy.☆76Mar 19, 2026Updated 6 months ago
- This is an IDE for YSYX_NPC debuging☆12Dec 10, 2024Updated last year
- 21st century electronic design automation tools, written in Rust.☆37Updated this week
- HardCaml example designs☆18Jun 13, 2018Updated 8 years ago
- A collection of datapath circuit design and verification benchmarks☆19Aug 24, 2026Updated last month
- The binaries for SaxonSoc Linux and other configurations☆18Mar 23, 2023Updated 3 years ago