Alternatives and similar repositories for verilated-rs:

Users that are interested in verilated-rs are comparing it to the libraries listed below

• ekiwi / wellen
  wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.
  ☆48Updated 2 weeks ago
• kevinmehall / rust-vcd
  Read and write VCD (Value Change Dump) files in Rust
  ☆43Updated last year
• fabianschuiki / llhd-sim
  The LLHD reference simulator.
  ☆37Updated 4 years ago
• Coloquinte / quaigh
  Logic circuit analysis and optimization
  ☆33Updated 5 months ago
• vegaluisjose / vast
  Verilog AST
  ☆21Updated last year
• ekiwi / fst-reader
  Native Rust implementation of the FST waveform format from GTKWave.
  ☆12Updated last month
• ThePerfectComputer / FastWaveBackend
  A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.
  ☆43Updated 2 months ago
• amaranth-lang / amaranth-soc
  System on Chip toolkit for Amaranth HDL
  ☆86Updated 5 months ago
• lachlansneff / ligeia
  A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.
  ☆19Updated 2 years ago
• calyxir / calyx-riscv
  RISCV Core written in Calyx
  ☆15Updated 7 months ago
• fabianschuiki / moore
  A hardware compiler based on LLHD and CIRCT
  ☆256Updated last year
• benbr8 / rstb
  Rust Test Bench - write HDL tests in Rust.
  ☆23Updated 2 years ago
• Kuree / hgdb
  Hardware generator debugger
  ☆73Updated last year
• chipsalliance / fpga-interchange-schema
  ☆55Updated 2 years ago
• apl-cornell / PDL
  A Hardware Pipeline Description Language
  ☆44Updated last year
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆55Updated 5 months ago
• chipsalliance / espresso
  ☆38Updated last year
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆51Updated last week
• CTSRD-CHERI / SIMTight
  Synthesisable SIMT-style RISC-V GPGPU
  ☆32Updated last month
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆59Updated 4 months ago
• yupferris / kaze
  An HDL embedded in Rust.
  ☆197Updated last year
• tcr / rust-verilog
  Verilog parsing and generator crate.
  ☆20Updated 4 years ago
• CTSRD-CHERI / TestRIG
  Testing processors with Random Instruction Generation
  ☆35Updated last week
• uenoku / firtool-standalone-plugin
  an experiment to run plugin in firtool pipeline
  ☆9Updated last year
• Kuree / fsim
  Fiber-based SystemVerilog Simulator.
  ☆25Updated 2 years ago
• litex-hub / pythondata-cpu-rocket
  Python module containing verilog files for rocket cpu (for use with LiteX).
  ☆13Updated 2 months ago
• Kuree / kratos
  Debuggable hardware generator
  ☆68Updated 2 years ago
• riscv-software-src / riscof
  ☆72Updated 5 months ago