efabless / chipignite-resourcesLinks
☆83Updated 2 years ago
Alternatives and similar repositories for chipignite-resources
Users that are interested in chipignite-resources are comparing it to the libraries listed below
Sorting:
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆44Updated 4 years ago
- XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.☆64Updated last week
- JKU IIC OSIC-Multitool for open-source IC (OSIC) design for SKY130.☆71Updated 5 months ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆156Updated 2 months ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆74Updated 4 years ago
- FOSS-ASIC-TOOLS is all in one container for SKY130 based design both Analog and Digital. Below is a list of the current tools already ins…☆99Updated last year
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆65Updated 2 years ago
- ☆115Updated 2 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆118Updated last year
- ☆42Updated 3 years ago
- Version manager (and builder) for the Google sky130 and gf180mcu open-source PDKs☆72Updated last month
- 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…☆116Updated 4 years ago
- ☆55Updated last year
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆76Updated 4 years ago
- IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)☆188Updated 3 months ago
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆137Updated 3 years ago
- A complete open-source design-for-testing (DFT) Solution☆164Updated 2 weeks ago
- ☆84Updated 7 months ago
- ☆43Updated 6 months ago
- ☆52Updated 5 months ago
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆42Updated 3 years ago
- SystemVerilog frontend for Yosys☆157Updated last week
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆163Updated 2 years ago
- ☆49Updated 7 months ago
- OpenROAD users should look at this repository first for instructions on getting started☆101Updated 4 years ago
- Circuit Automatic Characterization Engine☆51Updated 7 months ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆48Updated 4 years ago
- Home of the open-source EDA course.☆43Updated 3 months ago
- ☆171Updated 4 years ago
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆27Updated 4 years ago