steveicarus / simbus
Icarus SIMBUS
☆18Updated 5 years ago
Alternatives and similar repositories for simbus:
Users that are interested in simbus are comparing it to the libraries listed below
- Small footprint and configurable Inter-Chip communication cores☆55Updated 2 weeks ago
- Cross compile FPGA tools☆22Updated 4 years ago
- an inverter drawn in magic with makefile to simulate☆26Updated 2 years ago
- Notes, scripts and apps to quickfeather board☆10Updated 3 years ago
- a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface☆32Updated 3 years ago
- Board and connector definition files for nMigen☆30Updated 4 years ago
- Using VexRiscv without installing Scala☆37Updated 3 years ago
- RISC-V Processor written in Amaranth HDL☆36Updated 3 years ago
- An example OMI Device FPGA with 2 DDR4 memory ports☆16Updated 2 years ago
- Benchmarks for Yosys development☆23Updated 5 years ago
- Co-simulation and behavioural verification with VHDL, C/C++ and Python/m☆13Updated last week
- USB 1.1 Device IP Core☆20Updated 7 years ago
- Digital Circuit rendering engine☆37Updated last year
- RISC-V processor☆28Updated 2 years ago
- Open source hardware down to the chip level!☆30Updated 3 years ago
- SoftCPU/SoC engine-V☆54Updated last year
- A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga☆26Updated 5 years ago
- This repository contains iCEBreaker examples for Amaranth HDL.☆38Updated last year
- Bit streams forthe Ulx3s ECP5 device☆16Updated last year
- System on Chip toolkit for nMigen☆19Updated 4 years ago
- ☆33Updated 2 years ago
- A configurable USB 2.0 device core☆30Updated 4 years ago
- A padring generator for ASICs☆25Updated last year
- ULX2S / ULX3S FPGA JTAG programmer & tools (Lattice XP2 / ECP5)☆22Updated 3 months ago
- Simplified environment for litex☆14Updated 4 years ago
- A reconfigurable logic circuit made of identical rotatable tiles.☆21Updated 3 years ago
- Picorv32 SoC that uses only BRAM, not flash memory☆12Updated 6 years ago
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆20Updated last year
- Open Processor Architecture☆26Updated 8 years ago