Alternatives and similar repositories for simbus:

Users that are interested in simbus are comparing it to the libraries listed below

• gsomlo / yoloRISC
  A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga
  ☆26Updated 5 years ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆55Updated last month
• mmicko / cross-fpga
  Cross compile FPGA tools
  ☆22Updated 4 years ago
• mattvenn / magic-inverter
  an inverter drawn in magic with makefile to simulate
  ☆26Updated 2 years ago
• trabucayre / quickfeather-notes
  Notes, scripts and apps to quickfeather board
  ☆10Updated 3 years ago
• www-asics-ws / usb1_device
  USB 1.1 Device IP Core
  ☆18Updated 7 years ago
• OpenCAPI / omi_device_ice
  An example OMI Device FPGA with 2 DDR4 memory ports
  ☆16Updated 2 years ago
• greatscottgadgets / bucatini
  a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface
  ☆32Updated 3 years ago
• xobs / lxbuildenv
  Simplified environment for litex
  ☆14Updated 4 years ago
• RTimothyEdwards / irsim
  IRSIM switch-level simulator for digital circuits
  ☆31Updated 9 months ago
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆23Updated 5 years ago
• verilator / verilator_ext_tests
  Extended and external tests for Verilator testing
  ☆16Updated this week
• hdl-util / i2c
  Fully featured implementation of Inter-IC (I2C) bus master for FPGAs
  ☆26Updated 4 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆37Updated 3 years ago
• wavedrom / vcd-samples
  sample VCD files
  ☆36Updated last year
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆50Updated last year
• The-OpenROAD-Project / OpenROAD-Cloud
  The source code that empowers OpenROAD Cloud
  ☆12Updated 4 years ago
• daveshah1 / flow-examples
  Misc open FPGA flow examples
  ☆8Updated 5 years ago
• chipsalliance / f4pga-bitstream-viewer
  Tool for graphically viewing FPGA bitstream files and their connection to FASM features.
  ☆14Updated 2 years ago
• b224hisl / rioschip
  ☆33Updated 2 years ago
• ZipCPU / wbhyperram
  A cross platform, formally verified, open source, hyperRAM controller with simulator
  ☆11Updated 6 years ago
• efabless / caravel-lite
  ☆15Updated 3 months ago
• YosysHQ / prjtrellis-db
  Project Trellis database
  ☆13Updated last year
• whitequark / icefloorplan
  iCE40 floorplan viewer
  ☆24Updated 6 years ago
• umarcor / SIEAV
  Co-simulation and behavioural verification with VHDL, C/C++ and Python/m
  ☆13Updated this week
• lawrie / tiny_ram_soc
  Picorv32 SoC that uses only BRAM, not flash memory
  ☆12Updated 6 years ago
• antmicro / verilator-dynamic-scheduler-examples
  ☆22Updated last year
• wyvernSemi / usbModel
  USB virtual model in C++ for Verilog
  ☆29Updated 4 months ago
• ArcaneNibble / project-chibi
  Altera MAX V bitstream documentation -- CLEANUP PENDING
  ☆19Updated 4 years ago
• m-labs / nmigen-soc
  System on Chip toolkit for nMigen
  ☆19Updated 4 years ago