steveicarus / simbus
Icarus SIMBUS
☆17Updated 4 years ago
Related projects: ⓘ
- ☆11Updated this week
- ☆20Updated this week
- An example OMI Device FPGA with 2 DDR4 memory ports☆15Updated last year
- Small footprint and configurable Inter-Chip communication cores☆53Updated this week
- Notes, scripts and apps to quickfeather board☆10Updated 2 years ago
- Using VexRiscv without installing Scala☆34Updated 2 years ago
- Cross compile FPGA tools☆22Updated 3 years ago
- A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga☆24Updated 5 years ago
- IRSIM switch-level simulator for digital circuits☆30Updated 4 months ago
- iCE40 floorplan viewer☆24Updated 6 years ago
- Altera MAX V bitstream documentation -- CLEANUP PENDING☆19Updated 4 years ago
- a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface☆31Updated 2 years ago
- an inverter drawn in magic with makefile to simulate☆26Updated 2 years ago
- Simplified environment for litex☆13Updated 3 years ago
- USB 1.1 Device IP Core☆18Updated 6 years ago
- Finding the bacteria in rotting FPGA designs.☆13Updated 3 years ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆49Updated last year
- Misc open FPGA flow examples☆8Updated 4 years ago
- OpenFPGA☆33Updated 6 years ago
- CMod-S6 SoC☆35Updated 6 years ago
- A wishbone controlled FM transmitter hack☆21Updated 8 months ago
- Simulation VCD waveform viewer, using old Motif UI☆24Updated last year
- System on Chip toolkit for nMigen☆19Updated 4 years ago
- Standard HyperRAM core for ECP5 written in Litex/Migen☆14Updated 4 years ago
- The source code that empowers OpenROAD Cloud☆11Updated 4 years ago
- Repository and Wiki for Chip Hack events.☆50Updated 3 years ago
- A bit-serial CPU☆18Updated 4 years ago
- ULX2S / ULX3S FPGA JTAG programmer & tools (Lattice XP2 / ECP5)☆22Updated 4 months ago
- Yosys Plugins☆20Updated 5 years ago
- There are many RISC V projects on iCE40. This one is mine.☆13Updated 4 years ago