Alternatives and similar repositories for Computer-Architecture-Task-2

Users that are interested in Computer-Architecture-Task-2 are comparing it to the libraries listed below

• plctlab / writing-your-first-riscv-simulator
  《从零开始的RISC-V模拟器开发》配套的PPT和教学资料
  ☆227Updated 4 years ago
• MaxXSoft / Fuxi
  Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.
  ☆174Updated 4 years ago
• OSCPU / NutShell-doc
  ☆123Updated 3 years ago
• hehao98 / RISCV-Simulator
  A Simple RISC-V CPU Simulator with 5 Stage Pipeline, Branch Prediction and Cache Simulation
  ☆192Updated last year
• zach0zhang / Single_instruction_cycle_OpenMIPS
  通过学习《自己动手写CPU》，将书中实现的兼容MIPS32指令集架构的处理器——OpenMIPS（五级流水线结构），简化成单指令周期实现的处理器
  ☆206Updated 3 years ago
• OpenXiangShan / NEMU
  Super fast RISC-V ISA emulator for XiangShan processor
  ☆291Updated 2 weeks ago
• cnrv / riscv-soc-book
  关于RISC-V你所需要知道的一切
  ☆561Updated 2 years ago
• runninglinuxkernel / riscv_programming_practice
  ☆218Updated 2 years ago
• Lingrui98 / RISC-V-book
  A translation project of the RISC-V reader
  ☆175Updated last year
• OSCPU / ysyx
  一生一芯的信息发布和内容网站
  ☆133Updated last year
• skyzh / RISCV-Simulator
  💻 RISC-V Simulator of RV32I ISA. 5-stage pipeline / out-of-order execution with Tomasulo algorithm and Speculation. Support runtime visu…
  ☆206Updated 5 years ago
• LiHao217 / RISC-V_article_paper_src
  riscv资料、论文等
  ☆143Updated 6 years ago
• trivialmips / TrivialMIPS
  MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support
  ☆108Updated 6 years ago
• YanB25 / Tomasulo
  An out-of-order execution algorithm for pipeline CPU, implemented by verilog
  ☆42Updated 7 years ago
• whik / e200_opensource
  The Ultra-Low Power RISC Core
  ☆49Updated 6 years ago
• VenciFreeman / RISC-V
  A simple RISC-V CPU written in Verilog.
  ☆66Updated last year
• sunshaoce / learning-riscv
  入门RISC-V的手册
  ☆60Updated last year
• Trinkle23897 / mips32-cpu
  奋战一学期，造台计算机（编译出的bit文件在release中，可以直接食用）
  ☆129Updated 5 years ago
• cnrv / home
  为推广RISC-V尽些薄力
  ☆313Updated 2 years ago
• NJU-ProjectN / fceux-am
  ☆100Updated 10 months ago
• CNLHC / Awesome-RISC-V
  ☆29Updated 7 years ago
• z4yx / NaiveMIPS-HDL
  Naïve MIPS32 SoC implementation
  ☆116Updated 5 years ago
• NJU-ProjectN / nvboard
  NJU Virtual Board
  ☆291Updated 3 weeks ago
• trivialmips / nontrivial-mips
  NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.
  ☆600Updated 5 years ago
• f0rm2l1n / riscv-simulator-guide
  RISC-V模拟器，相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册
  ☆53Updated 5 years ago
• LvNA-system / labeled-RISC-V
  ☆167Updated 4 years ago
• jensen-yan / kisscpu
  国科大一生一芯第二期: RISCV-64 五级流水线CPU
  ☆18Updated 4 years ago
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆180Updated 11 months ago
• TuringKi / Gitbook-Computer-Architecture-A-Quantitative-Approach-6th-Chinese
  【持续更新中】计算机体系结构：量化研究方法（第六版）汉化
  ☆38Updated 3 years ago
• Z-Y00 / Examples-in-book-write-your-own-cpu
  《自己动手写CPU》一书附带的文件
  ☆87Updated 7 years ago