Alternatives and similar repositories for Computer-Architecture-Task-2

Users that are interested in Computer-Architecture-Task-2 are comparing it to the libraries listed below

• plctlab / writing-your-first-riscv-simulator
  《从零开始的RISC-V模拟器开发》配套的PPT和教学资料
  ☆224Updated 3 years ago
• cnrv / riscv-soc-book
  关于RISC-V你所需要知道的一切
  ☆563Updated 2 years ago
• hehao98 / RISCV-Simulator
  A Simple RISC-V CPU Simulator with 5 Stage Pipeline, Branch Prediction and Cache Simulation
  ☆186Updated last year
• MaxXSoft / Fuxi
  Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.
  ☆173Updated 4 years ago
• zach0zhang / Single_instruction_cycle_OpenMIPS
  通过学习《自己动手写CPU》，将书中实现的兼容MIPS32指令集架构的处理器——OpenMIPS（五级流水线结构），简化成单指令周期实现的处理器
  ☆207Updated 3 years ago
• OSCPU / NutShell-doc
  ☆122Updated 3 years ago
• runninglinuxkernel / riscv_programming_practice
  ☆212Updated last year
• OpenXiangShan / NEMU
  ☆288Updated this week
• Lingrui98 / RISC-V-book
  A translation project of the RISC-V reader
  ☆175Updated last year
• OSCPU / ysyx
  一生一芯的信息发布和内容网站
  ☆132Updated last year
• YanB25 / Tomasulo
  An out-of-order execution algorithm for pipeline CPU, implemented by verilog
  ☆40Updated 7 years ago
• cnrv / home
  为推广RISC-V尽些薄力
  ☆311Updated 2 years ago
• skyzh / RISCV-Simulator
  💻 RISC-V Simulator of RV32I ISA. 5-stage pipeline / out-of-order execution with Tomasulo algorithm and Speculation. Support runtime visu…
  ☆201Updated 5 years ago
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆176Updated 9 months ago
• LiHao217 / RISC-V_article_paper_src
  riscv资料、论文等
  ☆143Updated 6 years ago
• jianzhang96 / AZPRcpu
  AZPR cpu.《CPU自制入门》附录的Verilog代码，其中的日文注释翻译成了中文。
  ☆42Updated 5 years ago
• NJU-ProjectN / fceux-am
  ☆97Updated 8 months ago
• NJU-ProjectN / nvboard
  NJU Virtual Board
  ☆285Updated 3 weeks ago
• z4yx / NaiveMIPS-HDL
  Naïve MIPS32 SoC implementation
  ☆115Updated 5 years ago
• sunshaoce / learning-riscv
  入门RISC-V的手册
  ☆60Updated 11 months ago
• f0rm2l1n / riscv-simulator-guide
  RISC-V模拟器，相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册
  ☆53Updated 5 years ago
• LvNA-system / labeled-RISC-V
  ☆169Updated 4 years ago
• trivialmips / TrivialMIPS
  MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support
  ☆106Updated 6 years ago
• trivialmips / nontrivial-mips
  NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.
  ☆603Updated 5 years ago
• kaitoukito / A-Primer-on-Memory-Consistency-and-Cache-Coherence
  A Primer on Memory Consistency and Cache Coherence (Second Edition) 翻译计划
  ☆271Updated last year
• luzhixing12345 / archlab
  NUDT 高级体系结构实验
  ☆35Updated 10 months ago
• RickyTino / MangoMIPS32
  A softcore microprocessor of MIPS32 architecture.
  ☆40Updated last year
• whik / e200_opensource
  The Ultra-Low Power RISC Core
  ☆48Updated 5 years ago
• USTC-System-Courses / CECS-Lab
  ☆38Updated last year
• sunshaoce / rvcc-course
  ☆90Updated last year