Alternatives and similar repositories for RISCV-CPU

Users that are interested in RISCV-CPU are comparing it to the libraries listed below

• CherrySprings / CherrySprings
  ☆19Updated 2 years ago
• chsgcxy / messy_notes
  all kind of notes, I maybe sort this in the future
  ☆13Updated 3 months ago
• TYOD-SOC / RISCV-Accelerator
  ☆37Updated 7 years ago
• alireza-shirzad / Cordic_tanh
  Verilog and matlab implementation of tanh using Cordic algorithm
  ☆11Updated 5 years ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆40Updated 3 years ago
• OSCPU / yosys-sta
  ☆86Updated 2 weeks ago
• pulp-platform / cluster_interconnect
  ☆15Updated last month
• kaitoukito / YSYX-NJU-Group
  YSYX RISC-V Project NJU Study Group
  ☆16Updated 10 months ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆53Updated 3 years ago
• RPTU-EIS / RISCV-Core
  5-stage RISC-V core (RV32IM) with pipelining designed for educational purposes by RPTU Kaiserslautern, Germany
  ☆13Updated last year
• lizhirui / DreamCore
  ☆64Updated 3 years ago
• Heresyrac / Gemmini_doc
  关于移植模型至gemmini的文档
  ☆32Updated 3 years ago
• wangeddie67 / ESYSim
  ☆39Updated last year
• YanB25 / Tomasulo
  An out-of-order execution algorithm for pipeline CPU, implemented by verilog
  ☆42Updated 7 years ago
• xjtuiair-cag / SiYuan
  A RISC-V Symmetric Multiprocessor(SMP) based on TileLink and can run Linux OS
  ☆31Updated last month
• OSCPU / ysyxSoC
  ☆89Updated 2 months ago
• yutxie / cpu-riscv
  ACM Class 2017 Computer Architecture
  ☆10Updated 7 years ago
• Yawei-Ding / ysyx_riscv64_cpu
  ☆70Updated 2 years ago
• hyoukjun / OpenSMART
  Public release
  ☆58Updated 6 years ago
• sxtyzhangzk / mips-cpu
  A MIPS CPU implemented in Verilog
  ☆70Updated 8 years ago
• OpenXiangShan / XS-Verilog-Library
  ☆45Updated 3 years ago
• zhangzek / Clock-Domain-Crossing-Design
  Clock Domain Crossing Design（use MCP formulation without feedback）基于MCP不带反馈的跨时钟域设计
  ☆12Updated 5 years ago
• meton-robean / ResearchNote
  通过issue和README来记录日常学习研究笔记 关注 机器学习系统，深度学习， LLVM，性能剖视， Linux操作系统内核 话题 关注 C/C++. JAVA. Python. Golang. Chisel. 编程语言话题 ( Writing Blogs using …
  ☆78Updated 5 years ago
• microdynamics-cpu / tree-core-cpu
  A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …
  ☆44Updated 2 years ago
• KevinWang96 / Chip-Multi-processor-System-based-on-Cardinal-Bidirectional-Ring-Network-on-chip
  EE577b-Course-Project
  ☆19Updated 5 years ago
• xdesigns / 4way-cache
  Verilog cache implementation of 4-way FIFO 16k Cache
  ☆20Updated 12 years ago
• Jpz-sdju / trinity
  ☆32Updated 4 months ago
• light-ly / chisel-template
  自建 chisel 工程模板
  ☆14Updated 2 years ago
• jm2000 / RISCV-FPU
  Basic floating-point components for RISC-V processors
  ☆11Updated 8 years ago
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆37Updated 4 years ago