cquwei-cx / cpu20220108
MIPS 57条指令五级流水线cpu (verilog实现+详细注释)
☆11Updated 3 years ago
Alternatives and similar repositories for cpu20220108:
Users that are interested in cpu20220108 are comparing it to the libraries listed below
- 计算机体系结构研讨课 2020年秋季 UCAS 《CPU 设计实战》 Lab3-Lab9☆26Updated 3 years ago
- 重庆大学计算机学院2018级计算机体系结构cache设计☆12Updated 4 years ago
- 编译原理作业与实验☆9Updated 3 years ago
- 计算机体系结构研讨课 2020秋季 UCAS 《CPU设计实战》 工程环境及 RTL 代码合集☆17Updated 3 years ago
- 2020龙芯杯个人赛 简易双发射60M(含ibuffer)☆34Updated 4 years ago
- Chongqing University 2020 NSCSCC☆28Updated 4 years ago
- A 5-level pipelined MIPS CPU with branch prediction and great cache.☆19Updated 3 years ago
- 2022年龙芯杯个人赛 单发射110M(含icache)☆44Updated 2 years ago
- UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.☆124Updated 8 months ago
- 复旦大学FDU1.1队在第四届“龙芯杯”的参赛作品☆42Updated 4 years ago
- A LoongArch pipeline CPU. Project of Computer Architecture Lab @UCAS.☆20Updated 9 months ago
- CQU Dual Issue Machine☆35Updated 8 months ago
- 一生一芯 , ysyx , npc . the repo of the YSYX project . a riscv-64 CPU . writing .☆26Updated 2 years ago
- 国科大一生一芯第二期: RISCV-64 五级流水线CPU☆17Updated 3 years ago
- "aura" my super-scalar O3 cpu core☆24Updated 9 months ago
- 体系结构课程实验:RISC-V 32I 流水线 CPU,实现37条指令,转发,冒险检测,Cache,分支预测器☆72Updated 5 years ago
- ☆79Updated 3 weeks ago
- A RISC-V RV32I ISA Single Cycle CPU☆22Updated last year
- 龙芯杯个人赛工具包(适用于个人赛的golden_trace工具)☆48Updated last year
- ☆59Updated last year
- 为了更好地帮助后来的同学参加龙芯杯,草拟了这份建议,望对后来人有所帮助☆122Updated 4 years ago
- 重庆大学计算机组成原理、硬件综合设计实验材料。☆12Updated 2 years ago
- 重庆大学硬件综合设计课程实验文档☆39Updated last year
- 记录一下夏季学期计算机设计与实践课上写的RISC-V单周期CPU和RISC-V五级流水线CPU☆12Updated 3 years ago
- ☆57Updated 2 months ago
- Pick your favorite language to verify your chip.☆39Updated this week
- 2022龙芯杯个人赛三等奖作品☆13Updated last year
- 复旦大学 数字逻辑与部件设计实验 2020秋☆46Updated 3 years ago
- 一个单发射五级静态流水CPU,采用龙芯32位精简版指令集,支持异常和中断处理,使用AXI总线接口,已集成TLB模块☆14Updated 2 years ago
- Asymmetric dual issue in-order microprocessor.☆34Updated 5 years ago