Lyncien / RISC-V-32ILinks
体系结构课程实验:RISC-V 32I 流水线 CPU,实现37条指令,转发,冒险检测,Cache,分支预测器
☆84Updated 5 years ago
Alternatives and similar repositories for RISC-V-32I
Users that are interested in RISC-V-32I are comparing it to the libraries listed below
Sorting:
- UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.☆139Updated last year
- 一生一芯 , ysyx , npc . the repo of the YSYX project . a riscv-64 CPU . writing .☆29Updated 3 years ago
- ☆68Updated 2 years ago
- Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC(精简指令集)CPU(中央处理器)简单结构和Verilog实现。☆148Updated 6 years ago
- 为了更好地帮助后来的同学参加龙芯杯,草拟了这份建议,望对后来人有所帮助☆126Updated 4 years ago
- ☆86Updated 3 months ago
- 计算机体系结构研讨课 2020年秋季 UCAS 《CPU 设计实战》 Lab3-Lab9☆30Updated 3 years ago
- A simple RISC-V CPU written in Verilog.☆65Updated 11 months ago
- RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.☆295Updated 7 years ago
- 乱序双发处理器,在2024年计算机系统能力大赛CPU赛道(龙芯杯)获二等奖,全国第四☆15Updated 11 months ago
- 体系结构研讨 + ysyx高阶大纲 (WIP☆176Updated 9 months ago
- ☆77Updated 3 months ago
- A RISC-V RV32I ISA Single Cycle CPU☆25Updated 2 months ago
- riscv指令集,单周期以及五级流水线CPU☆79Updated 6 months ago
- ☆66Updated last year
- A FPGA-supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL. Achieve good performance due to optimizations like branch p…☆9Updated 5 years ago
- CPU Design Based on RISCV ISA☆118Updated last year
- 复旦大学FDU1.1队在第四届“龙芯杯”的参赛作品☆43Updated 4 years ago
- This is my graduation project, a simple processor soft core, which implements RV32I ISA.☆17Updated 6 years ago
- A LoongArch pipeline CPU. Project of Computer Architecture Lab @UCAS.☆25Updated last year
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆51Updated 3 years ago
- 一生一芯RISCV处理器核代码仓库(包括相关工具)☆14Updated 10 months ago
- NSCSCC 信息整合☆251Updated 4 years ago
- 龙芯杯个人赛工具包(适用于个人赛的golden_trace工具)☆61Updated last year
- 计算机体系结构研讨课 2020秋季 UCAS 《CPU设计实战》 工程环境及 RTL 代码合集☆18Updated 3 years ago
- 【原创,已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计,FPGA三级存储子系统。☆115Updated 5 years ago
- Asymmetric dual issue in-order microprocessor.☆34Updated 5 years ago
- Collect some IC textbooks for learning.☆150Updated 2 years ago
- ☆64Updated 2 years ago
- Verilog实现单周期非流水线32位RISCV指令集(45条)CPU☆42Updated 4 years ago