howardlau1999 / flapga-mario
FlaPGA Mario - A flappy-bird like video game implemented in Verilog for Basys3
☆29Updated 6 years ago
Alternatives and similar repositories for flapga-mario
Users that are interested in flapga-mario are comparing it to the libraries listed below
Sorting:
- ☆64Updated 2 years ago
- Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.☆172Updated 3 years ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆51Updated 2 years ago
- ☆86Updated 2 weeks ago
- a training-target implementation of rv32im, designed to be simple and easy to understand☆58Updated 3 years ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated last year
- An out-of-order execution algorithm for pipeline CPU, implemented by verilog☆40Updated 7 years ago
- ☆67Updated 3 months ago
- A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)☆118Updated 2 years ago
- ☆64Updated 3 weeks ago
- ☆31Updated 2 months ago
- 一生一芯CPU/目前做到cache/后续主要考虑ASIC DV☆20Updated 4 months ago
- A softcore microprocessor of MIPS32 architecture.☆39Updated 10 months ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆62Updated 3 years ago
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆49Updated 6 months ago
- LoveLonelyTime's RISC-V core basic version, RV32I, five pipeline stages.☆17Updated last year
- Asymmetric dual issue in-order microprocessor.☆34Updated 5 years ago
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆40Updated last year
- a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog☆47Updated last year
- Various caches written in Verilog-HDL☆123Updated 10 years ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆212Updated 4 years ago
- A small SoC with a pipeline 32-bit RISC-V CPU.☆63Updated 2 years ago
- ☆18Updated 2 years ago
- ☆66Updated 9 months ago
- ☆36Updated 6 years ago
- Open source high performance IEEE-754 floating unit☆72Updated last year
- MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support☆106Updated 6 years ago
- Modern co-simulation framework for RISC-V CPUs☆142Updated last week
- Open-source high-performance non-blocking cache☆81Updated 3 weeks ago
- "aura" my super-scalar O3 cpu core☆24Updated 11 months ago