Wren6991 / DOOMSoCLinks
A SoC for DOOM
☆17Updated 4 years ago
Alternatives and similar repositories for DOOMSoC
Users that are interested in DOOMSoC are comparing it to the libraries listed below
Sorting:
- Example Verilog code for Ulx3s☆40Updated 3 years ago
- PLEASE MOVE TO PAWSv2☆17Updated 3 years ago
- A simple risc-v CPU /GPU running on an Arty A7-100T FPGA board☆29Updated 3 years ago
- Programs for the FOMU, DE10NANO and ULX3S FPGA boards, written in Silice https://github.com/sylefeb/Silice☆35Updated last year
- VGA-compatible text mode functionality☆17Updated 5 years ago
- Picorv32 SoC that uses only BRAM, not flash memory☆13Updated 6 years ago
- Fully featured implementation of Inter-IC (I2C) bus master for FPGAs☆27Updated 5 years ago
- Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.☆60Updated 3 years ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- Reusable Verilog 2005 components for FPGA designs☆43Updated 3 months ago
- SoftCPU/SoC engine-V☆54Updated 2 months ago
- A reconfigurable logic circuit made of identical rotatable tiles.☆21Updated 3 years ago
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆21Updated last year
- shdl6800: A 6800 processor written in SpinalHDL☆26Updated 5 years ago
- Next-Generation FPGA Place-and-Route☆10Updated 6 years ago
- RISC-V RV32E core designed for minimal area☆16Updated 6 months ago
- ☆33Updated 2 years ago
- RISCV CPU implementation tutorial steps for Cologne Chip Gatemate E1, adopted from https://github.com/BrunoLevy/learn-fpga☆12Updated 3 months ago
- Cross compile FPGA tools☆22Updated 4 years ago
- soft processor core compatible with i586 instruction set(Intel Pentium) developped on Nexys4 board boots linux kernel with a ramdisk cont…☆32Updated 8 years ago
- simple wishbone client to read buttons and write leds☆18Updated last year
- ☆15Updated 2 weeks ago
- Quickly update a bitstream with new RAM contents☆15Updated 3 years ago
- Dual-core RISC-V SoC with JTAG, atomics, SDRAM☆25Updated 3 years ago
- ☆16Updated 3 weeks ago
- Bit streams forthe Ulx3s ECP5 device☆17Updated 2 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆12Updated 2 years ago
- Simplified environment for litex☆14Updated 4 years ago
- mystorm sram test☆27Updated 7 years ago
- CologneChip GateMate FPGA Module: GMM-7550☆22Updated this week