Wren6991 / DOOMSoCLinks
A SoC for DOOM
☆19Updated 4 years ago
Alternatives and similar repositories for DOOMSoC
Users that are interested in DOOMSoC are comparing it to the libraries listed below
Sorting:
- A simple risc-v CPU /GPU running on an Arty A7-100T FPGA board☆31Updated 4 years ago
- Reusable Verilog 2005 components for FPGA designs☆48Updated 8 months ago
- FPGA based microcomputer sandbox for software and RTL experimentation☆71Updated last week
- FPGA GPU design for DE1-SoC☆73Updated 3 years ago
- A Risc-V SoC for Tiny Tapeout☆43Updated last month
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆69Updated 3 years ago
- Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.☆62Updated 4 years ago
- 5-stage RISC-V CPU, originally developed for RISCBoy☆34Updated 2 years ago
- A computer (FPGA SoC) based on the MRISC32-A1 CPU☆54Updated 2 years ago
- ☆71Updated last year
- Dual-issue RV64IM processor for fun & learning☆64Updated 2 years ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆108Updated 2 months ago
- A collection of SPI related cores☆19Updated last year
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆81Updated 5 years ago
- IEEE 754 single precision floating point library in systemverilog and vhdl☆38Updated 10 months ago
- USB virtual model in C++ for Verilog☆32Updated last year
- An open source FPGA PCI core & 8250-Compatible PCI UART core☆44Updated 4 years ago
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆54Updated last year
- Picorv32 SoC that uses only BRAM, not flash memory☆13Updated 6 years ago
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆22Updated 2 years ago
- A pipelined RISC-V processor☆62Updated last year
- Latest in the line of the E32 processors with better/generic cache placement☆10Updated 2 years ago
- Using VexRiscv without installing Scala☆39Updated 4 years ago
- RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).☆20Updated 4 months ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆38Updated last year
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆33Updated 8 months ago
- Basic OpenGL 1.x implementation for small FPGAs (like iCE40UP5K)☆39Updated 3 years ago
- Portable HyperRAM controller☆60Updated 11 months ago
- ☆15Updated 5 months ago
- SoftCPU/SoC engine-V☆55Updated 7 months ago