Alternatives and similar repositories for NetworkOnChip

Users that are interested in NetworkOnChip are comparing it to the libraries listed below

• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆36Updated 4 years ago
• hyoukjun / microswitch-noc
  ☆27Updated 6 years ago
• ljgibbslf / basic_cache_core
  ☆29Updated 5 years ago
• matutani / nocgen
  NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers
  ☆67Updated 5 years ago
• Youssefmdany / Design-and-UVM-TB-of-RISC-V-Microprocessor
  Design and UVM-TB of RISC -V Microprocessor
  ☆28Updated last year
• openhwgroup / core-v-mcu-uvm
  CORE-V MCU UVM Environment and Test Bench
  ☆24Updated last year
• jmjos / ratatoskr
  Ratatoskr NoC Simulator
  ☆28Updated 4 years ago
• ic-lab-duth / DRIM
  DUTH RISC-V Microprocessor
  ☆22Updated 10 months ago
• Liu-Cheng / cycle-accurate-SystemC-simulator-over-ramulator
  An example of using Ramulator as memory model in a cycle-accurate SystemC Design
  ☆53Updated 8 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆60Updated last year
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆59Updated last week
• SingularityKChen / SystemC-Training
  SystemC training aimed at TLM.
  ☆32Updated 5 years ago
• EngAhmed21 / RISC-V-Processor-with-Pipelining
  Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…
  ☆15Updated last year
• kuladeepsaireddy / OpenNoc
  ☆37Updated 6 years ago
• frobino / Nostrum-SystemC-simulator
  SystemC simulator of a highly customizable Nostrum network-on-chip (NoC).
  ☆14Updated 11 years ago
• Arteris-IP / tlm2-interfaces
  contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols
  ☆63Updated last month
• chipsalliance / aib-protocols
  ☆27Updated last year
• pulp-platform / axi_llc
  ☆30Updated last month
• Nikola2444 / RISC-V-vector-processor
  ☆15Updated 3 years ago
• ultraembedded / core_axi_cache
  128KB AXI cache (32-bit in, 256-bit out)
  ☆53Updated 4 years ago
• bsc-loca / sauria
  SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…
  ☆61Updated last year
• DreamCloud-Project / McSim-TLM-NoC
  Manycore platform Simulation tool for NoC-based platform at a Transactional Level Modeling level
  ☆10Updated 9 years ago
• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆18Updated last year
• StanfordAHA / AhaM3SoC
  SoC Based on ARM Cortex-M3
  ☆33Updated 5 months ago
• cornell-brg / pymtl3-net
  Project repo for the POSH on-chip network generator
  ☆51Updated 7 months ago
• ics-jku / riscv-vp-plusplus
  RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…
  ☆43Updated last week
• Muriukidavid / systemc-examples
  A repository for SystemC Learning examples
  ☆71Updated 3 years ago
• tej-chavan / Design-and-Verification-of-DDR3-Memory-Controller
  The memory model was leveraged from micron.
  ☆24Updated 7 years ago
• LCAI-TIHU / HW
  LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…
  ☆42Updated 2 years ago
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆42Updated 4 years ago