jessebarreto / NetworkOnChipLinks
Development of a Network on Chip Simulation using SystemC.
☆33Updated 8 years ago
Alternatives and similar repositories for NetworkOnChip
Users that are interested in NetworkOnChip are comparing it to the libraries listed below
Sorting:
- HLS for Networks-on-Chip☆37Updated 4 years ago
- ☆28Updated 6 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆17Updated last year
- DUTH RISC-V Microprocessor☆22Updated last year
- SystemC simulator of a highly customizable Nostrum network-on-chip (NoC).☆14Updated 11 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆71Updated 5 years ago
- Ratatoskr NoC Simulator☆28Updated 4 years ago
- SystemC training aimed at TLM.☆34Updated 5 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆55Updated 8 years ago
- Design and UVM-TB of RISC -V Microprocessor☆30Updated last year
- ☆32Updated last week
- General Purpose AXI Direct Memory Access☆61Updated last year
- ☆31Updated 5 years ago
- CORE-V MCU UVM Environment and Test Bench☆24Updated last year
- Project repo for the POSH on-chip network generator☆52Updated 8 months ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated this week
- Andes Vector Extension support added to riscv-dv☆17Updated 5 years ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆47Updated last month
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆63Updated last week
- Constrained RAndom Verification Enviroment (CRAVE)☆18Updated 2 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆32Updated 6 months ago
- ☆38Updated 6 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆68Updated last week
- SoC Based on ARM Cortex-M3☆34Updated 6 months ago
- ☆15Updated 3 years ago
- Xilinx AXI VIP example of use☆42Updated 4 years ago
- ☆57Updated 6 years ago
- SystemVerilog modules and classes commonly used for verification☆51Updated last week
- ☆12Updated last month
- Public release☆58Updated 6 years ago