jessebarreto / NetworkOnChipLinks
Development of a Network on Chip Simulation using SystemC.
☆34Updated 8 years ago
Alternatives and similar repositories for NetworkOnChip
Users that are interested in NetworkOnChip are comparing it to the libraries listed below
Sorting:
- HLS for Networks-on-Chip☆35Updated 4 years ago
- ☆27Updated 5 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆66Updated 5 years ago
- DUTH RISC-V Microprocessor☆20Updated 8 months ago
- ☆34Updated 6 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆51Updated 8 years ago
- General Purpose AXI Direct Memory Access☆57Updated last year
- Andes Vector Extension support added to riscv-dv☆17Updated 5 years ago
- ☆29Updated 4 years ago
- ☆14Updated 2 years ago
- Ratatoskr NoC Simulator☆27Updated 4 years ago
- SystemC simulator of a highly customizable Nostrum network-on-chip (NoC).☆14Updated 11 years ago
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆58Updated 2 weeks ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆58Updated 2 weeks ago
- SystemC training aimed at TLM.☆31Updated 5 years ago
- Design and UVM-TB of RISC -V Microprocessor☆23Updated last year
- RTL code of some arbitration algorithm☆14Updated 5 years ago
- ☆26Updated last year
- CORE-V MCU UVM Environment and Test Bench☆21Updated last year
- A repository for SystemC Learning examples☆70Updated 2 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆30Updated 2 months ago
- OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.☆14Updated 4 months ago
- SoC Based on ARM Cortex-M3☆32Updated 2 months ago
- Connecting SystemC with SystemVerilog☆41Updated 13 years ago
- ☆52Updated 6 years ago
- ☆30Updated 2 weeks ago
- Constrained RAndom Verification Enviroment (CRAVE)☆17Updated last year
- Xilinx AXI VIP example of use☆41Updated 4 years ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 9 months ago