jessebarreto / NetworkOnChipLinks
Development of a Network on Chip Simulation using SystemC.
☆32Updated 7 years ago
Alternatives and similar repositories for NetworkOnChip
Users that are interested in NetworkOnChip are comparing it to the libraries listed below
Sorting:
- SystemC training aimed at TLM.☆29Updated 4 years ago
- Ratatoskr NoC Simulator☆26Updated 4 years ago
- ☆27Updated 5 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆50Updated 7 years ago
- HLS for Networks-on-Chip☆34Updated 4 years ago
- ☆28Updated 4 years ago
- General Purpose AXI Direct Memory Access☆50Updated last year
- SystemC simulator of a highly customizable Nostrum network-on-chip (NoC).☆14Updated 11 years ago
- ☆14Updated 2 years ago
- Constrained RAndom Verification Enviroment (CRAVE)☆17Updated last year
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆56Updated this week
- The memory model was leveraged from micron.☆22Updated 7 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆28Updated 8 months ago
- ☆33Updated 6 years ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 7 months ago
- Xilinx AXI VIP example of use☆40Updated 4 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 5 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆37Updated 2 years ago
- Synopsys Design compiler, VCS and Tetra-MAX☆18Updated 7 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆49Updated 4 years ago
- LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.☆16Updated last year
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆55Updated last month
- AXI3 Bus Functional Models (Initiator & Target)☆28Updated 2 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆63Updated 5 years ago
- Project repo for the POSH on-chip network generator☆46Updated 2 months ago
- verification of simple axi-based cache☆18Updated 6 years ago
- ☆26Updated last year
- Advanced Architecture Labs with CVA6☆61Updated last year
- CORE-V eXtension Interface compliant RISC-V [F|Zfinx] Coprocessor☆11Updated 7 months ago
- The Verilog source code for DRUM approximate multiplier.☆31Updated 2 years ago