jessebarreto / NetworkOnChip
Development of a Network on Chip Simulation using SystemC.
☆31Updated 7 years ago
Alternatives and similar repositories for NetworkOnChip:
Users that are interested in NetworkOnChip are comparing it to the libraries listed below
- HLS for Networks-on-Chip☆34Updated 4 years ago
- SystemC training aimed at TLM.☆28Updated 4 years ago
- Ratatoskr NoC Simulator☆24Updated 4 years ago
- ☆26Updated 5 years ago
- SystemC simulator of a highly customizable Nostrum network-on-chip (NoC).☆14Updated 10 years ago
- Project repo for the POSH on-chip network generator☆45Updated 3 weeks ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆53Updated last month
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆49Updated 7 years ago
- Constrained RAndom Verification Enviroment (CRAVE)☆17Updated last year
- ☆31Updated 5 years ago
- Xilinx AXI VIP example of use☆37Updated 3 years ago
- General Purpose AXI Direct Memory Access☆49Updated 11 months ago
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆55Updated 2 weeks ago
- LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.☆16Updated 11 months ago
- ☆26Updated 4 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆25Updated 4 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆36Updated 2 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆64Updated 2 months ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆61Updated 5 years ago
- cycle accurate Network-on-Chip Simulator☆27Updated last year
- Connecting SystemC with SystemVerilog☆40Updated 13 years ago
- Manycore platform Simulation tool for NoC-based platform at a Transactional Level Modeling level☆10Updated 8 years ago
- BlackParrot on Zynq☆38Updated last month
- Andes Vector Extension support added to riscv-dv☆14Updated 4 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆48Updated 3 years ago
- DUTH RISC-V Microprocessor☆18Updated 4 months ago
- ☆43Updated 6 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆26Updated 6 months ago
- ☆25Updated last year
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆21Updated 6 years ago