jessebarreto / NetworkOnChip
Development of a Network on Chip Simulation using SystemC.
☆31Updated 7 years ago
Alternatives and similar repositories for NetworkOnChip:
Users that are interested in NetworkOnChip are comparing it to the libraries listed below
- HLS for Networks-on-Chip☆33Updated 4 years ago
- SystemC simulator of a highly customizable Nostrum network-on-chip (NoC).☆14Updated 10 years ago
- Ratatoskr NoC Simulator☆24Updated 3 years ago
- ☆24Updated 5 years ago
- SystemC training aimed at TLM.☆27Updated 4 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆50Updated this week
- ☆25Updated last year
- Constrained RAndom Verification Enviroment (CRAVE)☆17Updated last year
- ☆41Updated 6 years ago
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆55Updated last month
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆48Updated 7 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆25Updated 4 months ago
- An Open-Hardware CGRA for accelerated computation on the edge.☆16Updated 5 months ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆59Updated 5 years ago
- General Purpose AXI Direct Memory Access☆48Updated 9 months ago
- ☆25Updated 4 years ago
- ☆29Updated 5 years ago
- ☆70Updated 10 years ago
- DUTH RISC-V Microprocessor☆19Updated 2 months ago
- cycle accurate Network-on-Chip Simulator☆25Updated last year
- Design and UVM-TB of RISC -V Microprocessor☆14Updated 7 months ago
- ☆12Updated 2 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆36Updated 2 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆30Updated last month
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 4 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆17Updated 5 months ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆40Updated 4 years ago
- LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.☆14Updated 9 months ago