Alternatives and similar repositories for NetworkOnChip:

Users that are interested in NetworkOnChip are comparing it to the libraries listed below

• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆33Updated 4 years ago
• hyoukjun / microswitch-noc
  ☆26Updated 5 years ago
• SingularityKChen / SystemC-Training
  SystemC training aimed at TLM.
  ☆27Updated 4 years ago
• Liu-Cheng / cycle-accurate-SystemC-simulator-over-ramulator
  An example of using Ramulator as memory model in a cycle-accurate SystemC Design
  ☆49Updated 7 years ago
• jmjos / ratatoskr
  Ratatoskr NoC Simulator
  ☆24Updated 3 years ago
• frobino / Nostrum-SystemC-simulator
  SystemC simulator of a highly customizable Nostrum network-on-chip (NoC).
  ☆14Updated 10 years ago
• kuladeepsaireddy / OpenNoc
  ☆31Updated 5 years ago
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆52Updated last week
• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆17Updated last year
• matutani / nocgen
  NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers
  ☆60Updated 5 years ago
• Arteris-IP / tlm2-interfaces
  contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols
  ☆56Updated last month
• ljgibbslf / basic_cache_core
  ☆26Updated 4 years ago
• muzafferkal / axi-bfm
  AXI3 Bus Functional Models (Initiator & Target)
  ☆28Updated 2 years ago
• chipsalliance / aib-protocols
  ☆25Updated last year
• LCAI-TIHU / HW
  LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…
  ☆36Updated 2 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆49Updated 10 months ago
• Nikola2444 / RISC-V-vector-processor
  ☆13Updated 2 years ago
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆30Updated 5 months ago
• pulp-platform / fpu
  ☆41Updated 6 years ago
• pulp-platform / common_verification
  SystemVerilog modules and classes commonly used for verification
  ☆46Updated 2 months ago
• hlslibs / ac_ml
  Algorithmic C Machine Learning Library
  ☆22Updated 3 months ago
• vlsi-lab / len5
  LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.
  ☆15Updated 10 months ago
• Minres / SystemC-Components
  A SystemC productivity library: https://minres.github.io/SystemC-Components/
  ☆103Updated last week
• cornell-brg / pymtl3-net
  Project repo for the POSH on-chip network generator
  ☆44Updated last week
• chad-q / andes-vector-riscv-dv
  Andes Vector Extension support added to riscv-dv
  ☆14Updated 4 years ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆40Updated 2 years ago
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆41Updated 4 years ago
• adki / DPI_Tutorial
  SystemVerilog Direct Programming Interface (DPI) Tutorial
  ☆53Updated 4 years ago
• anan-cn / Open-Source-Network-on-Chip-Router-RTL
  ☆71Updated 10 years ago
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆25Updated 5 months ago