Alternatives and similar repositories for Readings-in-Computer-Architectures

Users that are interested in Readings-in-Computer-Architectures are comparing it to the libraries listed below

• TeCSAR-UNCC / gem5-SALAM
  ☆92Updated last year
• Davxx / gem5_Garnet2.0_extensions
  Fork of the gem5 simulator with Garnet2.0 and DSENT extensions
  ☆11Updated 6 years ago
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆65Updated last year
• tukl-msd / gem5.TnT
  gem5 Tips & Tricks
  ☆70Updated 5 years ago
• qiyancos / gem5-with-chinese-comment
  Gem5 with chinese comment and introduction (master) and some other std gem5 version.
  ☆42Updated 3 years ago
• gem5bootcamp / 2024
  Materials, slides, and workspace for the gem5 bootcamp 2024
  ☆36Updated 11 months ago
• tancheng / CGRA-Mapper
  An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.
  ☆73Updated this week
• lshpku / gem5-fs-handbook
  gem5 FS模式实验手册
  ☆43Updated 2 years ago
• synxlin / branch-predictor-simulator
  A C version of Branch Predictor Simulator
  ☆18Updated last year
• ecolab-nus / morpher
  An Open-Source Tool for CGRA Accelerators
  ☆67Updated 3 months ago
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆57Updated 3 years ago
• ramisheikh / cbp2025
  Championship Branch Prediction 2025
  ☆49Updated 2 months ago
• SingularityKChen / SystemC-Training
  SystemC training aimed at TLM.
  ☆30Updated 4 years ago
• chenhaoc / ESL_Learning
  some knowleage about SystemC/TLM etc.
  ☆25Updated 2 years ago
• pku-dasys / pillars
  An integrated CGRA design framework
  ☆90Updated 4 months ago
• Chun-Feng / CACTI-6.5
  This tools offer many simulation of memory design detail parameter. Then you can setting these parameter to running result in your condit…
  ☆16Updated 9 years ago
• Liu-Cheng / cycle-accurate-SystemC-simulator-over-ramulator
  An example of using Ramulator as memory model in a cycle-accurate SystemC Design
  ☆51Updated 8 years ago
• CMU-SAFARI / PiDRAM
  PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …
  ☆69Updated last year
• alexmr09 / Mixed-precision-Neural-Networks-on-RISC-V-Cores
  ☆31Updated 2 months ago
• OpenXiangShan / GEM5
  ☆90Updated last week
• jieltan / OpenCompArchCourse
  ☆22Updated 4 years ago
• cry-daniel / Computer-Architecture-Learning
  ☆62Updated 2 years ago
• pulp-platform / ITA
  ☆47Updated 3 months ago
• CMU-SAFARI / Hermes
  A speculative mechanism to accelerate long-latency off-chip load requests by removing on-chip cache access latency from their critical pa…
  ☆72Updated 10 months ago
• baichen318 / arch-explorer
  ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis
  ☆32Updated last year
• lizhirui / DreamCoreV2
  ☆22Updated 2 years ago
• jmjos / ratatoskr
  Ratatoskr NoC Simulator
  ☆27Updated 4 years ago
• PrincetonUniversity / muchiSim
  Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…
  ☆68Updated last year
• cwfletcher / buffets
  Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.
  ☆75Updated 6 years ago
• HewlettPackard / mcpat
  An integrated power, area, and timing modeling framework for multicore and manycore architectures
  ☆190Updated 4 years ago