OldRepoPreservation / mpeg2fpgaLinks
An MPEG2 video decoder, written in Verilog and implemented in an FPGA chip.
☆24Updated 6 years ago
Alternatives and similar repositories for mpeg2fpga
Users that are interested in mpeg2fpga are comparing it to the libraries listed below
Sorting:
- Ethernet MAC 10/100 Mbps☆27Updated 3 years ago
- USB 1.1 Host and Function IP core☆23Updated 10 years ago
- DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.☆55Updated last year
- An open source FPGA PCI core & 8250-Compatible PCI UART core☆42Updated 4 years ago
- Master-thesis-final☆19Updated last year
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆38Updated last year
- MMC (and derivative standards) host controller☆24Updated 4 years ago
- AXI-4 RAM Tester Component☆17Updated 4 years ago
- IEEE 754 single precision floating point library in systemverilog and vhdl☆30Updated 6 months ago
- Use an MPSSE FTDI device as a JTAG interface in Quartus tools☆22Updated last year
- USB capture IP☆21Updated 5 years ago
- Minimal DVI / HDMI Framebuffer☆82Updated 4 years ago
- USB -> AXI Debug Bridge☆39Updated 4 years ago
- Mini CPU design with JTAG UART support☆20Updated 4 years ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- Fully featured implementation of Inter-IC (I2C) bus master for FPGAs☆27Updated 5 years ago
- ULPI Link Wrapper (USB Phy Interface)☆28Updated 5 years ago
- USB 2.0 FS Device controller IP core written in SystemVerilog☆36Updated 6 years ago
- Wishbone interconnect utilities☆41Updated 4 months ago
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆27Updated 4 months ago
- Repo that shows how to use the VexRiscv with OpenOCD and semihosting.☆25Updated 3 years ago
- USB serial device (CDC-ACM)☆39Updated 4 years ago
- Reusable Verilog 2005 components for FPGA designs☆44Updated 4 months ago
- Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface☆22Updated 7 years ago
- ☆19Updated 6 years ago
- FT2232HL JTAG & UART Downloader☆15Updated 3 years ago
- turbo 8051☆29Updated 7 years ago
- Designing and implementing LZ4 decompression algorithm in hardware (FPGA) using Verilog hardware description language☆16Updated 6 years ago
- SDIO Device Verilog Core☆22Updated 6 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆90Updated 5 years ago