Hardware and software implementation of Sparsely-active SNNs
☆22Mar 6, 2026Updated 2 weeks ago
Alternatives and similar repositories for SNN-DSE
Users that are interested in SNN-DSE are comparing it to the libraries listed below
Sorting:
- MIPS Processor, BNN Accelerator, AXI4 interface, Cache Controller and LRU replacement☆13Nov 4, 2022Updated 3 years ago
- CORDIC-SNN, followed with "Unsupervised learning of digital recognition using STDP" published in 2015, frontiers☆25Feb 9, 2020Updated 6 years ago
- Code for the ISCAS23 paper "The Hardware Impact of Quantization and Pruning for Weights in Spiking Neural Networks"☆11Apr 20, 2023Updated 2 years ago
- CS4362 - Hardware Description Languages. Implemented SNN on an FPGA for real-time image processing using VHDL☆24Dec 29, 2023Updated 2 years ago
- Here is the official code for ICASSP 2024 "Optimal ANN-SNN Conversion with Group Neurons".☆14Mar 1, 2024Updated 2 years ago
- Implementation of a Systolic Array based sorting engine on an FPGA using Verilog☆11May 11, 2017Updated 8 years ago
- The code of SpikingSSMs: Learning Long Sequences with Sparse and Parallel Spiking State Space Models☆22Apr 16, 2025Updated 11 months ago
- Ternary Spike: Learning Ternary Spikes for Spiking Neural Networks☆27Dec 14, 2023Updated 2 years ago
- Framework for radix encoded SNN on FPGA☆18Dec 7, 2021Updated 4 years ago
- The official implementation of HPCA 2025 paper, Prosperity: Accelerating Spiking Neural Networks via Product Sparsity☆38Aug 9, 2025Updated 7 months ago
- ☆56Jan 29, 2024Updated 2 years ago
- Pipelined FFT/IFFT 64 points processor☆11Jul 17, 2014Updated 11 years ago
- R2MDC FFT/IFFT processor adaptive to 64/128/256/512 point☆18Dec 23, 2025Updated 2 months ago
- A small Neural Network Processor for Edge devices.☆18Nov 22, 2022Updated 3 years ago
- Spiking neural network inference engine for 7-Series FPGAs☆27Aug 31, 2025Updated 6 months ago
- [FPL 2021] SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs.☆64Jul 28, 2021Updated 4 years ago
- Tensor Processing Unit implementation in Verilog☆13Mar 18, 2025Updated last year
- An energy simulation framework for BPTT-based SNN inference and training.☆17Sep 6, 2023Updated 2 years ago
- SCARIF is a tool to estimate the embodied carbon emissions of data center servers with accelerator hardware (GPUs, FPGAs, etc.)☆15Updated this week
- 一个支持AXI总线、支持Cache、包括所有非浮点MIPS 1指令、支持例外的静态五级流水MIPS CPU☆11Oct 8, 2019Updated 6 years ago
- 基于k210的2021电赛F题数字识别☆16Dec 4, 2021Updated 4 years ago
- ☆20Dec 14, 2023Updated 2 years ago
- Router 1 x 3 verilog implementation☆15Sep 5, 2021Updated 4 years ago
- ZC RISCV CORE☆12Dec 19, 2019Updated 6 years ago
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆39Jun 14, 2019Updated 6 years ago
- Offical Implementation of "CLIF: Complementary Leaky Integrate-and-Fire Neuron for Spiking Neural Networks" (ICML 2024 spotlight)☆27Sep 17, 2025Updated 6 months ago
- A 2D mesh Network on Chip with 5-stage pipelined router, all implemented in Verilog and run on Artix-7 FPGA.☆17May 30, 2023Updated 2 years ago
- Simulating implement of LeNet network on Zynq-7020 FPGA☆30Mar 11, 2019Updated 7 years ago
- Offical implementation of "Quantized Spike-driven Transformer" (ICLR2025)☆34Dec 23, 2025Updated 2 months ago
- [TVLSI'23] This repository contains the source code for the paper "FireFly: A High-Throughput Hardware Accelerator for Spiking Neural Net…☆24Apr 4, 2024Updated last year
- tinyODIN digital spiking neural network (SNN) processor - HDL source code and documentation.☆76Mar 30, 2023Updated 2 years ago
- Simulator for LLM inference on an abstract 3D AIMC-based accelerator☆26Sep 18, 2025Updated 6 months ago
- PIM-ML is a benchmark for training machine learning algorithms on the UPMEM architecture, which is the first publicly-available real-worl…☆25Jan 7, 2025Updated last year
- Update arXiv papers about Spiking Neural Networks daily.☆491Updated this week
- ☆31Aug 8, 2020Updated 5 years ago
- Deep SNNs with various neural coding methods (rate, phase, burst, TTFS)☆12Feb 15, 2022Updated 4 years ago
- HLS code for a BNN accelerator☆17Sep 13, 2018Updated 7 years ago
- IEEE Transactions on Circuits and Systems I: Efficient FPGA Implementations of Pair and Triplet-based STDP for Neuromorphic Architectures☆29Jul 7, 2019Updated 6 years ago
- HedgeHog Fused Spiking Neural Network Emulator/Compute Engine is a hardware implementation of a SNN designed for implementation in Xilinx…☆60Feb 10, 2026Updated last month