Alternatives and similar repositories for SNN-DSE

Users that are interested in SNN-DSE are comparing it to the libraries listed below

• BaoBao-zhu / RV-SCNN
  A Custom RISC-V Instruction Extension for SNN and CNN Computation
  ☆29Updated last year
• saunak1994 / CyNAPSEv11
  The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL
  ☆36Updated 6 years ago
• Angela-WangBo / Shenjing-RTL
  This is the RTL implementation of Shenjing, a low power neuromorphic computing accelerator
  ☆17Updated 5 years ago
• snagiri / CSE237D-PYNQ-SNN-Accelerator
  Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board
  ☆39Updated 6 years ago
• oshears / SNN-FPGA-Implementation
  ☆20Updated 4 years ago
• HanPU-Code / CNN_YOLO_AI_accelerator
  This project is to design yolo AI accelerator in verilog HDL.
  ☆28Updated last year
• Spiritator / FPGA_LeNet5_ws_8x8
  FPGA implement of 8x8 weight stationary systolic array DNN accelerator
  ☆16Updated 4 years ago
• Minz9 / SNN-on-FPGA
  SNN on FPGA
  ☆11Updated 3 years ago
• evan199893 / TPU_systolic_array_HW_accelerator
  Tensor Processing Unit implementation in Verilog
  ☆11Updated 9 months ago
• jerry-D / HedgeHog-Fused-Spiking-Neural-Network-Emulator-Compute-Engine
  HedgeHog Fused Spiking Neural Network Emulator/Compute Engine is a hardware implementation of a SNN designed for implementation in Xilinx…
  ☆60Updated 10 months ago
• DanielGerlinghoff / radix-encoding
  Framework for radix encoded SNN on FPGA
  ☆18Updated 4 years ago
• hazooree / LeNet-CNN-Accelerator-Hardware-for-FPGA
  An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017
  ☆20Updated 6 years ago
• Intelligent-Microsystems-Lab / SNNQuantPrune
  Code for the ISCAS23 paper "The Hardware Impact of Quantization and Pruning for Weights in Spiking Neural Networks"
  ☆11Updated 2 years ago
• zwhexplorer / Spiking-Neural-Network-Accelerator-EE552-project
  Spiking Neural Network Accelerator
  ☆15Updated 3 years ago
• Bhagya-laxmi / nn_noxim
  Network on chip based neural network accelerator
  ☆10Updated 4 years ago
• VincentWang1998 / ai_on_chip_project1
  tpu-systolic-array-weight-stationary
  ☆25Updated 4 years ago
• 8krisv / CNN-ACCELERATOR
  Hardware accelerator for convolutional neural networks
  ☆61Updated 3 years ago
• SFU-HiAccel / SyncNN
  [FPL 2021] SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs.
  ☆64Updated 4 years ago
• booniebears / CoMN
  ☆18Updated last year
• arkhodamoradi / s2n2
  ☆17Updated 4 years ago
• KyleParkJong / Network-on-Chip-Simulator
  Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator
  ☆36Updated 2 years ago
• wzc810049078 / systolic-array-matrix-multiplier
  A systolic array matrix multiplier
  ☆30Updated 6 years ago
• cepdnaclk / e17-4yp-Neuromorphic-NoC-Architecture-for-SNNs
  This project aims to develop a novel neuromorphic NoC architecture based on RISC-V ISA to support spiking neural network applications, an…
  ☆21Updated last month
• Stanzzz77 / SNN-NEST_Simulator_2.14.0-xilinx-ZCU102
  A nest brain simulator based on FPGA(LIF NEURON)
  ☆15Updated 4 years ago
• BoChen-Ye / Tiny_LeViT_Hardware_Accelerator
  This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.
  ☆27Updated last year
• hsieh672 / SNN-Accelerator
  A three-layer LIF neuron SNN accelerator. The first layer is the input layer and has 784 neurons, that receive the encoded spikes. The se…
  ☆14Updated 2 years ago
• sweetwenwen / Stochastic-computing-based-neural-network-accelerator
  ☆11Updated 6 years ago
• Deepak42074 / SRAM_IMC_MPW8
  The project includes SRAM In Memory Computing Accelerator with updates in design/circuits submitted previously in MPW7, by IITD researche…
  ☆16Updated 3 years ago
• dubcyfor3 / Prosperity
  The official implementation of HPCA 2025 paper, Prosperity: Accelerating Spiking Neural Networks via Product Sparsity
  ☆36Updated 5 months ago
• hyupupup / conv_systolic_array
  (Verilog) A simple convolution layer implementation with systolic array structure
  ☆13Updated 3 years ago