Digital IC design and vlsi notes
☆13Jun 24, 2020Updated 5 years ago
Alternatives and similar repositories for vlsi-notes
Users that are interested in vlsi-notes are comparing it to the libraries listed below
Sorting:
- ☆14May 15, 2023Updated 2 years ago
- Implementation of the Snappy compression algorithm as a RoCC accelerator☆12Jul 29, 2019Updated 6 years ago
- A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…☆17Sep 5, 2019Updated 6 years ago
- CVA6 softcore contest☆22Mar 9, 2026Updated last week
- CNN accelerator using NoC architecture☆18Dec 6, 2018Updated 7 years ago
- Final Project for Digital Systems Design Course, Fall 2020☆17Jul 20, 2022Updated 3 years ago
- This project is designed to delay the output of the video stream in AXI-STREAM format.☆12Jul 14, 2024Updated last year
- This is a SpyDrNet Plugin for a physical design related transformations☆16Jun 13, 2025Updated 9 months ago
- This repository contains a SystemVerilog implementation of a parametrized Round Robin arbiter with three instantiation options☆13Jan 28, 2024Updated 2 years ago
- RiVer Core is an open source Python based RISC-V Core Verification framework.☆23Jun 16, 2025Updated 9 months ago
- An open source 3GPP LTE implementation. (GitHub import of https://sourceforge.net/projects/openlte/)☆10Mar 7, 2017Updated 9 years ago
- ☆21Nov 12, 2025Updated 4 months ago
- Public repository to host our Checker IP written in SVA that is ported to run on open-source Verilator.☆12Mar 31, 2023Updated 2 years ago
- APB UVC ported to Verilator☆11Nov 19, 2023Updated 2 years ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆28Nov 21, 2019Updated 6 years ago
- Open-source Neural Processing Unit (NPU) from China ❤☆39Jan 29, 2025Updated last year
- PSA-ADAC SDC-600 Secure Debug Manager library for authenticated debug☆15Mar 18, 2025Updated last year
- Standalone Access Registration (SAR) is the process by which a device registers with a 5G network to gain access to its services. It invo…☆23Mar 25, 2023Updated 2 years ago
- RTL data structure☆64Feb 20, 2026Updated last month
- A template-based, layer-oriented High Level Synthesis Tool for AI algorithms☆13Mar 12, 2026Updated last week
- Final project for Computer Architecture FA16☆20Jan 5, 2017Updated 9 years ago
- VHDL sources for a BT.656 to axi4-stream converter☆12Mar 20, 2023Updated 3 years ago
- 3-wide superscalar, out-of-order RISC-V processor (RV32IM subset) in System Verilog, demonstrating key Instruction-Level Parallelism☆26Aug 15, 2025Updated 7 months ago
- UVM Auto Generate ; Verify Project Build; Verilog Instance☆35Apr 15, 2020Updated 5 years ago
- This repository provides a Linux kernel driver for AXI UART Lite accessed via PCIe XDMA. It enables efficient DMA-based UART communicatio…☆16May 2, 2025Updated 10 months ago
- PULP C910, a superscalar out-of-order RISC-V core adapted from T-Head's openC910 (Alibaba Group) and integrated into the PULP ecosystem w …☆15Jun 11, 2025Updated 9 months ago
- Template for project1 TPU☆23May 1, 2021Updated 4 years ago
- This project contains Verilog designs and a PCB for the implementation of CSI-2 camera interface to HDMI bridge on a Gatemate FPGA from C…☆19Jul 28, 2025Updated 7 months ago
- Design a median filter for a Generic RGB image.☆14Mar 6, 2019Updated 7 years ago
- A Toy-Purpose TPU Simulator☆22Jun 7, 2024Updated last year
- Neuromorphic ASIC with 96 neurons on Tiny Tapeout 7☆11May 25, 2024Updated last year
- Network on Chip for MPSoC☆28Feb 28, 2026Updated 2 weeks ago
- ☆35Jun 9, 2022Updated 3 years ago
- Yilong's NetFPGA-10G Repo☆12May 7, 2015Updated 10 years ago
- tpu-systolic-array-weight-stationary☆25May 7, 2021Updated 4 years ago
- TUM EI7402 SystemC laboratory assignments☆11Aug 10, 2021Updated 4 years ago
- This document is a project of cmos image sensor system. The doc mainly includes LUPA4000 Cmos sensor driving, SDRAM storage, LVDS data re…☆12Feb 7, 2021Updated 5 years ago
- We are aimed at making a device for shooting real-time HDR (High Dynamic Range) video using FPGA.☆31May 18, 2019Updated 6 years ago
- DUTH RISC-V Superscalar Microprocessor☆34Oct 23, 2024Updated last year