ahegazy / vlsi-notesLinks
Digital IC design and vlsi notes
☆12Updated 5 years ago
Alternatives and similar repositories for vlsi-notes
Users that are interested in vlsi-notes are comparing it to the libraries listed below
Sorting:
- UVM resource from github, run simulation use YASAsim flow☆30Updated 5 years ago
- This repository contains an example of the connection between an UVM Testbench and a Python reference model using UVM Connect from Mentor…☆17Updated 5 years ago
- Generate a Verilog Source file and testbench file for a given Moore FSM☆17Updated 12 years ago
- ☆13Updated 7 months ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- Design and UVM-TB of RISC -V Microprocessor☆26Updated last year
- NoC based MPSoC☆11Updated 11 years ago
- ☆29Updated 5 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆19Updated 8 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆13Updated 2 years ago
- Verification IP for Watchdog☆11Updated 4 years ago
- Final Project for Digital Systems Design Course, Fall 2020☆14Updated 3 years ago
- ☆17Updated 10 years ago
- To design test bench of the APB protocol☆17Updated 4 years ago
- verification of simple axi-based cache☆18Updated 6 years ago
- OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.☆15Updated 6 months ago
- Router 1 x 3 verilog implementation☆14Updated 4 years ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆16Updated 2 years ago
- ☆12Updated 9 years ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆13Updated 9 years ago
- Implementation of the PCIe physical layer☆48Updated 2 months ago
- RTL code of some arbitration algorithm☆14Updated 6 years ago
- AXI4 with a FIFO integrated with VIP☆22Updated last year
- A python project to automatically generate the UVM testbench document.☆20Updated last year
- Systemverilog DPI-C call Python function☆26Updated 4 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆30Updated 3 months ago
- OpenExSys_NoC a mesh-based network on chip IP.☆16Updated last year
- Direct Access Memory for MPSoC☆13Updated 4 months ago
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆14Updated 5 years ago
- UVM Testbench for synchronus fifo☆17Updated 5 years ago