smartfoxdata / uvm_axi
uvm_axi is a uvm package for modeling and verifying AXI protocol
☆16Updated 2 months ago
Alternatives and similar repositories for uvm_axi:
Users that are interested in uvm_axi are comparing it to the libraries listed below
- UVM VIP architecture generator☆19Updated 4 years ago
- AHB-APB UVM Verification Environment☆17Updated 9 years ago
- Verification AXI-4 bus standard using UVM and System Verilog☆15Updated 7 years ago
- Verification IP for SPI protocol☆17Updated 4 years ago
- uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol☆22Updated 2 months ago
- Verification IP for APB protocol☆62Updated 4 years ago
- UART design in SV and verification using UVM and SV☆44Updated 5 years ago
- This repository contains an example of the use of UVM Register Abstraction Layer in a verification of a simple APB DUT.☆38Updated 4 years ago
- UVM Testbench for synchronus fifo☆16Updated 4 years ago
- ☆25Updated 3 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆31Updated 2 years ago
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆25Updated 2 years ago
- UVM register utility generation by inputting xls table☆36Updated last year
- System verilog register model for uvm testbenches.☆19Updated 6 years ago
- UVM resource from github, run simulation use YASAsim flow☆27Updated 5 years ago
- Synchronous FIFO design & verification using systemVerilog Assertions☆15Updated 3 years ago
- ☆40Updated last year
- Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence☆32Updated 4 years ago
- This is a open source project from UVM Community and it is based on an Ethernet Switch System-on-Chip (SoC).☆13Updated 3 years ago
- UVM testbench environment consisting of an APB driver, high level SPI controller model, and SPI verification testbench based upon an LPC2…☆10Updated 4 months ago
- generate UVM testbench using python☆27Updated 7 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆16Updated 10 years ago
- Implements a simple UVM based testbench for a simple memory DUT.☆12Updated 5 years ago
- Verification IP for APB protocol☆26Updated 4 years ago
- ☆21Updated 3 years ago
- Maven Silicon Project☆17Updated 6 years ago
- UVM Auto Generate ; Verify Project Build; Verilog Instance☆34Updated 5 years ago
- Sample UVM code for axi ram dut☆32Updated 3 years ago
- UVM APB VIP, part of AMBA3&AMBA4 feature supported☆31Updated 4 years ago
- The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a …☆17Updated 3 years ago