Alternatives and similar repositories for Viterbi-Algorithm

Users that are interested in Viterbi-Algorithm are comparing it to the libraries listed below

• AsFigo / apb_uvc_verilator
  APB UVC ported to Verilator
  ☆11Updated last year
• PeterMonsson / sv_waveterm
  ☆10Updated last year
• dpretet / bster
  Implementation of a binary search tree algorithm in a FPGA/ASIC IP
  ☆19Updated 4 years ago
• jerry-D / 64-bit-Universal-Floating-Point-ISA-Compute-Engine
  RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine
  ☆22Updated 3 years ago
• asyncvlsi / summer2022
  Summer School Week 1 & 2 repo
  ☆11Updated 3 years ago
• jfoshea / Viterbi-Decoder-in-Verilog
  An efficient implementation of the Viterbi decoding algorithm in Verilog
  ☆54Updated last year
• V0XNIHILI / parametrizable-floating-point-verilog
  Educational verilog library that supports IEEE754 floating point arithmetic with a parametrizable mantissa and exponent
  ☆29Updated 6 months ago
• coleblackman / TIDENet
  TIDENet is an ASIC written in Verilog for Tiny Image Detection at Edge with neural networks (TIDENet) using DNNWeaver 2.0, the Google Sky…
  ☆17Updated 2 years ago
• scale-lab / DRUM
  The Verilog source code for DRUM approximate multiplier.
  ☆31Updated 2 years ago
• CESNET / ofm
  Open FPGA Modules
  ☆24Updated 11 months ago
• uwemeyerbaese / DSP_with_FPGAs_ed4
  DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3
  ☆61Updated 3 years ago
• trivedidvijen / SPI-to-I2C-Protocol-Conversion-Using-Verilog
  SPI to I2C Protocol Conversion Using Verilog. Final Year BTech project. Also published an IEEE paper.
  ☆11Updated 4 years ago
• tom-urkin / AMBA
  AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog
  ☆15Updated 2 years ago
• FPGA-House-AG / SpinalCorundum
  SpinalHDL components for Corundum Ethernet
  ☆13Updated 2 years ago
• mashahedurrahman / Security-Engine
  ☆13Updated last year
• uwemeyerbaese / DSP_with_FPGAs_ed3
  DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8
  ☆15Updated 3 years ago
• eldrickm / wakey_wakey
  EE 272B - VLSI Design Project
  ☆13Updated 4 years ago
• hellgate202 / crc_calc
  Simple and effective parallel CRC calculator written in synthesizable SystemVerilog
  ☆14Updated 6 years ago
• liuguangxi / gng
  Gaussian noise generator Verilog IP core
  ☆31Updated 2 years ago
• RedFlag2017 / rs-codec
  Reed Solomon Encoder and Decoder Digital IP
  ☆21Updated 5 years ago
• efabless / raptor_soc_template
  Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.
  ☆22Updated 5 years ago
• suburaaj / Fpga-Implementation-of-Precise-Convolutional-Neural-Network-for-Extreme-Learning-Machine
  Feed-forward neural networks can be trained based on a gradient-descent based backpropagation algorithm. But, these algorithms require mo…
  ☆12Updated 5 years ago
• Mshivam2409 / LDPC-Decoder
  Implementation of Partially Parellel LDPC Code Decoder in Verilog
  ☆15Updated 5 years ago
• heyfey / sv-pathfinder
  VS Code extension for SystemVerilog design navigation and RTL tracing. Seamlessly integrates with waveform viewer for post-simulation deb…
  ☆23Updated 2 weeks ago
• Lcrypto / FEC-Archive-Verilog
  Verilog Forward Error Correction Archive: BOX-Muller for fast AWGN generation, Universal Demapper from BPSK to QAM-512, different Forward…
  ☆76Updated 2 years ago
• wnew / hdl_library
  A library of verilog and vhdl modules
  ☆15Updated 6 years ago
• hyoukjun / microswitch-noc
  ☆27Updated 5 years ago
• habibagamal / SoC_Automation
  SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …
  ☆39Updated 4 years ago
• ehw-fit / approx-fpgas
  Approximate arithmetic circuits for FPGAs
  ☆12Updated 5 years ago
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆21Updated 2 years ago