Alternatives and similar repositories for bisunaU50

Users that are interested in bisunaU50 are comparing it to the libraries listed below

• natu4u / GSOC_TensorCore
  TensorCore Vector Processor for Deep Learning - Google Summer of Code Project
  ☆22Updated 3 years ago
• bsc-loca / sauria
  SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…
  ☆46Updated 8 months ago
• lukasc-ch / ExtendedBitPlaneCompression
  Provides the code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators" by Luk…
  ☆19Updated 5 years ago
• ACADLab / SA-DS
  ☆11Updated 11 months ago
• sfu-arch / SpGEMM
  ☆35Updated 4 years ago
• harvard-acc / FlexASR
  FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
  ☆46Updated 4 months ago
• amin-norollah / PAT-Noxim
  cycle accurate Network-on-Chip Simulator
  ☆27Updated 2 years ago
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆65Updated 3 years ago
• jiaaom / HPDLA
  Systolic-array based Deep Learning Accelerator generator
  ☆25Updated 4 years ago
• AlexMontgomerie / samo
  SAMO: Streaming Architecture Mapping Optimisation
  ☆33Updated last year
• ehw-fit / tf-approximate
  Approximate layers - TensorFlow extension
  ☆27Updated 2 months ago
• Accelergy-Project / processing-in-memory-design
  ☆25Updated last year
• pulp-platform / stream-ebpc
  Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…
  ☆24Updated 4 years ago
• yzwangfeng / reram-synthesis
  A synthesis flow for hybrid processing-in-RRAM modes
  ☆12Updated 3 years ago
• GATECH-EIC / Auto-NBA
  [ICML 2021] "Auto-NBA: Efficient and Effective Search Over the Joint Space of Networks, Bitwidths, and Accelerators" by Yonggan Fu, Yonga…
  ☆16Updated 3 years ago
• jgoeders / dac_sdc_2020_designs
  Designs for finalist teams of the DAC System Design Contest
  ☆37Updated 4 years ago
• GATECH-EIC / AutoDNNchip
  ☆71Updated 5 years ago
• kkiningh / cs231n-project
  CNN accelerator
  ☆27Updated 8 years ago
• jgoeders / dac_sdc_2021
  ☆23Updated 3 years ago
• awai54st / LUTNet
  ☆58Updated 5 years ago
• jgoeders / dac_sdc_2021_designs
  ☆20Updated 3 years ago
• Hosseinabady / SDSoC-Benchmarks
  ☆16Updated 4 years ago
• PSCLab-ASU / Systolic-CNN
  ☆16Updated 4 years ago
• Xilinx / hydra
  ☆12Updated 3 years ago
• Sibylau / HLS_designs
  Systolic array implementations for Cholesky, LU, and QR decomposition
  ☆42Updated 7 months ago
• xliu0709 / WinoCNN
  An HLS based winograd systolic CNN accelerator
  ☆53Updated 3 years ago
• SameLight / ITRI-OpenDLA
  Express DLA implementation for FPGA, revised based on NVDLA.
  ☆9Updated 5 years ago
• microideax / T-DLA
  ☆19Updated 5 years ago
• awai54st / Logic-Shrinkage
  ☆23Updated 2 years ago
• hyoukjun / microswitch-noc
  ☆27Updated 5 years ago