Alternatives and similar repositories for toped

Users that are interested in toped are comparing it to the libraries listed below

• GMM-7550 / gmm7550-hardware
  CologneChip GateMate FPGA Module: GMM-7550
  ☆24Updated 3 weeks ago
• torc-isi / torc
  Torc: Tools for Open Reconfigurable Computing
  ☆39Updated 8 years ago
• mabrains / sky130_ubuntu_setup
  Ubuntu scripts that are used for setting up your machine for Sky130 designs.
  ☆18Updated 4 years ago
• YosysHQ / yosys-plugins
  Yosys Plugins
  ☆22Updated 6 years ago
• bunnie / netlist-checker
  EDIF netlist checker tool
  ☆26Updated 3 years ago
• dan-rodrigues / caravel_vdp_lite
  ☆20Updated 4 years ago
• stnolting / fpga_torture
  🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
  ☆31Updated 3 years ago
• freecores / udp_ip__core
  UDP/IP Core
  ☆12Updated 11 years ago
• tmeissner / vhdl_verification
  Examples and design pattern for VHDL verification
  ☆15Updated 9 years ago
• efabless / ravenna
  32-bit RISC-V microcontroller
  ☆12Updated 4 years ago
• diadatp / sky130_rf_tools
  Guides and templates for using open source RF design tools with the SkyWater SKY130 process.
  ☆19Updated 4 years ago
• tmeissner / libvhdl
  Library of reusable VHDL components
  ☆28Updated last year
• idea-fasoc / fasoc
  ☆56Updated 2 years ago
• The-OpenROAD-Project / OpenROAD-Cloud
  The source code that empowers OpenROAD Cloud
  ☆12Updated 5 years ago
• VLSI-EDA / PoC-Examples
  This repository contains synthesizable examples which use the PoC-Library.
  ☆38Updated 4 years ago
• tclarke / sky130radio
  components and examples for creating radio ICs using the open skywater 130nm PDK
  ☆19Updated 4 years ago
• noasic / noasic
  An open-source VHDL library for FPGA design.
  ☆32Updated 3 years ago
• carlos-jenkins / csv2vcd
  Signal analyzer CSV to IEEE 1364-2001 VCD file format converter.
  ☆11Updated 4 years ago
• mattvenn / logLUTs
  Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.
  ☆22Updated 2 years ago
• RTimothyEdwards / irsim
  IRSIM switch-level simulator for digital circuits
  ☆34Updated 6 months ago
• RTimothyEdwards / qrouter
  Qrouter detail router for digital ASIC designs
  ☆57Updated 7 months ago
• mattvenn / caravel_user_project
  Zero to ASIC group submission for MPW2
  ☆13Updated 7 months ago
• Featherweight-IP / fwrisc
  Featherweight RISC-V implementation
  ☆53Updated 3 years ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• jck / uhdl
  Utilities for MyHDL
  ☆19Updated last year
• bluecheetah / bag
  BAG framework
  ☆41Updated last year
• tilk / yosys2digitaljs
  Export netlists from Yosys to DigitalJS
  ☆51Updated 2 months ago
• freecores / udp_ip_stack
  1G eth UDP / IP Stack
  ☆10Updated 11 years ago
• udara28 / SDRAM_Controller
  Implementation of a SDRAM controller in MyHDL (http://www.myhdl.org/)
  ☆21Updated 9 years ago
• lawrie / tiny_ram_soc
  Picorv32 SoC that uses only BRAM, not flash memory
  ☆13Updated 6 years ago