☆93Aug 17, 2019Updated 7 years ago
Alternatives and similar repositories for process
Users that are interested in process are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A Qt5 based free VLSI development tool☆31Jun 24, 2018Updated 8 years ago
- 1st Testwafer for LibreSilicon☆28Aug 2, 2019Updated 7 years ago
- Copyleftist's Standard Cell Library☆105May 2, 2024Updated 2 years ago
- ☆31Aug 19, 2019Updated 7 years ago
- 1st Testwafer for LibreSilicon☆15May 24, 2019Updated 7 years ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- Verilog Modules for DSP functions and other common tasks to make FPGA development easier and more fun.☆20Jun 7, 2015Updated 11 years ago
- mojito☆13May 1, 2018Updated 8 years ago
- Project Trellis database☆16Sep 15, 2025Updated last year
- 64-bit MISC Architecture CPU☆13Dec 13, 2016Updated 9 years ago
- Provides a packaged collection of open source EDA tools☆12Apr 14, 2019Updated 7 years ago
- components and examples for creating radio ICs using the open skywater 130nm PDK☆18Nov 29, 2020Updated 5 years ago
- Covered is a Verilog code coverage utility using VCD/LXT/FST dumpfiles (or VPI interface) and the design to generate line, toggle, memory…☆31Oct 18, 2018Updated 7 years ago
- ☆13May 21, 2024Updated 2 years ago
- Provides dot visualizations of chisel/firrtl circuites☆13Mar 12, 2019Updated 7 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- A port of the DesignStart Cortex-M0 system to the Diligentinc Arty board☆13Sep 7, 2018Updated 8 years ago
- Resource-efficient 16-bit CPU architecture for FPGA control plane☆97Feb 20, 2025Updated last year
- Open Analog Design Environment☆27May 19, 2023Updated 3 years ago
- This project has files needed to design and characterise flipflop☆21Jun 3, 2019Updated 7 years ago
- 32-bit RISC-V microcontroller☆13Sep 11, 2021Updated 5 years ago
- This is the Google/EFabless/Skywater Caravel submission of an Analog Spiking Neuron Circuit. The submission also includes a SONOS transis…☆12Apr 21, 2023Updated 3 years ago
- A set of tools based on radare2 for analysis of ROP gadgets and payloads.☆15Apr 20, 2016Updated 10 years ago
- A tool for analysing the source-level static connectivity of a SystemVerilog design☆29Updated this week
- Gate-level visualization generator for SKY130-based chip designs.☆20Jul 22, 2021Updated 5 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- GCC for Xuantie RISC-V CPU, the GNU Compiler Collection.☆22Sep 16, 2026Updated 3 weeks ago
- Book on Dynamical Systems Approaches to Infectious Disease Epidemiology☆11Nov 30, 2021Updated 4 years ago
- ☆15Dec 2, 2021Updated 4 years ago
- Skywater 130nm Klayout Device Generators PDK☆31Jul 12, 2024Updated 2 years ago
- PID controller☆25Jul 17, 2014Updated 12 years ago
- ☆66Dec 16, 2018Updated 7 years ago
- Macsyma☆15Jan 23, 2018Updated 8 years ago
- EPWave -- The Free Interactive Browser-Based Wave Viewer☆14Apr 1, 2015Updated 11 years ago
- IO and periphery cells for the GF180MCU provided by GlobalFoundries.☆14Dec 3, 2022Updated 3 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- An SRAM IP Uniquely designed with open source tools. Static RAM is a type of random-access memory that uses latching circuitry (flip-flop…☆16Jul 22, 2020Updated 6 years ago
- UCSD Sizer for leakage/dynamic power recovery, timing recovery☆18Mar 5, 2019Updated 7 years ago
- Builds, flow and designs for the alpha release☆55Dec 18, 2019Updated 6 years ago
- Documenting the Xilinx 7-series bit-stream format.☆921Jun 5, 2025Updated last year
- An example OMI Device FPGA with 2 DDR4 memory ports☆20Jan 5, 2023Updated 3 years ago
- Library of Octave functions for continuous gravitational-wave data analysis☆12Feb 28, 2023Updated 3 years ago
- USB Full-Speed core written in migen/LiteX☆12Sep 19, 2019Updated 7 years ago