henjo / pyoa
Donald Amundson's Python interface to OpenAccess IC design data API
☆16Updated 14 years ago
Related projects ⓘ
Alternatives and complementary repositories for pyoa
- BAG framework☆41Updated 3 months ago
- Open Analog Design Environment☆22Updated last year
- A C++ VLSI circuit schematic and layout database library☆13Updated 4 months ago
- Interchange formats for chip design.☆27Updated 2 months ago
- ☆13Updated 6 months ago
- Automatic generation of real number models from analog circuits☆37Updated 7 months ago
- Python port of Prof. Boris Murmann's gm/ID Starter Kit☆51Updated 7 years ago
- Jupyter kernel for Cadence SKILL☆22Updated 7 years ago
- A Python and SKILL Framework for Cadence Virtuoso☆33Updated 8 months ago
- Cadence Virtuoso Design Management System☆33Updated 2 years ago
- A python3 gm/ID starter kit☆39Updated 2 months ago
- MOSIS MPW Test Data and SPICE Models Collections☆26Updated 4 years ago
- repository for a bandgap voltage reference in SKY130 technology☆34Updated last year
- Design of Analog Blocks in Skywaters 130nm meeting corners: different flavors of OTA, BandGap, LDO.☆26Updated 2 years ago
- This library is a low level parser for the OpenAccess file format.☆13Updated 7 years ago
- Files for Advanced Integrated Circuits☆26Updated last week
- skywater 130nm pdk☆26Updated last month
- Connect Cadence Virtuoso to a Python client using sockets.☆15Updated 4 years ago
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆21Updated last year
- A tiny Python package to parse spice raw data files.☆43Updated last year
- Verilog-A simulation models☆53Updated 3 weeks ago
- Skywater 130nm Klayout Device Generators PDK☆29Updated 4 months ago
- components and examples for creating radio ICs using the open skywater 130nm PDK☆17Updated 3 years ago
- This repository is for (pre-)release versions of the Revolution EDA.☆35Updated this week
- Parametric layout generator for digital, analog and mixed-signal integrated circuits☆49Updated this week
- Minimal SKY130 example with self-checking LVS, DRC, and PEX☆23Updated 3 years ago
- PLL Designs on Skywater 130nm MPW☆20Updated 11 months ago
- Custom IC Creator Simulation tools☆10Updated this week
- Reads a Cadence techfile into KLayout and produces layer properties from it☆23Updated last year