Donald Amundson's Python interface to OpenAccess IC design data API
☆19Apr 23, 2010Updated 16 years ago
Alternatives and similar repositories for pyoa
Users that are interested in pyoa are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A C++ VLSI circuit schematic and layout database library☆16Jul 1, 2024Updated 2 years ago
- This library is a low level parser for the OpenAccess file format.☆16Jun 24, 2017Updated 9 years ago
- Open Analog Design Environment☆26May 19, 2023Updated 3 years ago
- autorouter forked from https://www-soc.lip6.fr/git/coriolis.git☆15May 21, 2018Updated 8 years ago
- BAG framework☆44Jul 24, 2024Updated last year
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Cadence Virtuoso Design Management System☆38Nov 13, 2022Updated 3 years ago
- A seamless python to Cadence Virtuoso Skill interface☆326Mar 23, 2026Updated 3 months ago
- Cadence Virtuoso Git Integration written in SKILL++☆162Sep 3, 2022Updated 3 years ago
- MOSIS MPW Test Data and SPICE Models Collections☆42Apr 2, 2020Updated 6 years ago
- IP kung-FU☆10Mar 14, 2019Updated 7 years ago
- Circuit analysis environment for Python☆61Sep 6, 2024Updated last year
- An alternative PnR system, or at least an attempt to get it running on Ubuntu 18.04.☆10Aug 31, 2018Updated 7 years ago
- Inter Process Communication (IPC) between Python and Cadence Virtuoso☆83Dec 22, 2016Updated 9 years ago
- Magic VLSI Layout Tool☆21Oct 10, 2019Updated 6 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Advanced Integrated Circuits 2024☆24Nov 16, 2024Updated last year
- Parametric layout generator for digital, analog and mixed-signal integrated circuits☆81Jul 14, 2026Updated last week
- This package provides a gnucap based qucsator implementation.☆16May 13, 2026Updated 2 months ago
- A port of the MATLAB Delta Sigma Toolbox based on free software and very little sleep☆99Mar 6, 2022Updated 4 years ago
- A Python and SKILL Framework for Cadence Virtuoso☆55Dec 13, 2025Updated 7 months ago
- ☆51Feb 7, 2025Updated last year
- KLayout technology files for Skywater SKY130☆44Jul 19, 2023Updated 3 years ago
- Diary of the bluetooth thermal printer reverse engineering☆22Apr 24, 2022Updated 4 years ago
- KiCad RF Stuff☆14Aug 17, 2021Updated 4 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Designs for Process-Voltage-Temperature (PVT) Sensors with MCU☆25May 8, 2020Updated 6 years ago
- Git repository to manage the fixes I need to make to the alliance-5.0-20090901 source for Mac OS X compiles.☆17Jul 23, 2010Updated 15 years ago
- pcells for various magnetic passive devices (GPL v3)☆13Sep 21, 2013Updated 12 years ago
- Python enabled OpenSCAD☆19Oct 21, 2011Updated 14 years ago
- UCSD Sizer for leakage/dynamic power recovery, timing recovery☆18Mar 5, 2019Updated 7 years ago
- Generate SVG schematics and block diagrams without a mouse.☆34Jul 5, 2025Updated last year
- Netgen complete LVS tool for comparing SPICE or verilog netlists☆137Jul 7, 2026Updated 2 weeks ago
- Python port of Prof. Boris Murmann's gm/ID Starter Kit☆58Jun 30, 2017Updated 9 years ago
- A fully-integrated FT8 protocol receiver on 130nm CMOS☆57Nov 13, 2022Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆21Apr 19, 2024Updated 2 years ago
- python with flask☆10Jun 26, 2020Updated 6 years ago
- Python-to-schematic generator for Cadence Virtuoso. Define circuits in Python, auto-generate CDL netlists and schematics.☆26Jun 28, 2026Updated 3 weeks ago
- Interchange formats for chip design.☆39Feb 15, 2026Updated 5 months ago
- 12 bit SAR ADC IP in Skywater 130 nm PDK☆31May 30, 2024Updated 2 years ago
- ☆15Mar 16, 2023Updated 3 years ago
- This is the XDM netlist converter, used to convert PSPICE and HSPICE netists into Xyce format.☆25Feb 15, 2024Updated 2 years ago