Alternatives and similar repositories for cocotb-coverage

Users that are interested in cocotb-coverage are comparing it to the libraries listed below

• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆138Updated last week
• themperek / cocotb-test
  Unit testing for cocotb
  ☆166Updated 2 months ago
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆259Updated last year
• cocotb / cocotb-bus
  Pre-packaged testbenching tools and reusable bus interfaces for cocotb
  ☆75Updated this week
• svunit / svunit
  ☆209Updated 11 months ago
• raysalemi / Python4RTLVerification
  ☆176Updated 3 years ago
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆173Updated 2 months ago
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆74Updated 2 months ago
• olofk / ipyxact
  Python-based IP-XACT parser and utilities
  ☆143Updated last year
• amiq-consulting / svaunit
  SVAUnit is an UVM compliant package that simplify the creation of stimuli/checkers for validating SystemVerilog Assertions (SVA)
  ☆75Updated 5 years ago
• accellera / uvm
  ☆60Updated 9 years ago
• Juniper / open-register-design-tool
  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  ☆207Updated last year
• SystemRDL / systemrdl-compiler
  SystemRDL 2.0 language compiler front-end
  ☆271Updated 3 weeks ago
• accellera-official / uvm-core
  ☆114Updated last year
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆74Updated 4 months ago
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆311Updated 4 months ago
• cluelogic / cluelib
  A generic class library in SystemVerilog
  ☆87Updated 4 years ago
• AUCOHL / Fault
  A complete open-source design-for-testing (DFT) Solution
  ☆179Updated 5 months ago
• adki / DPI_Tutorial
  SystemVerilog Direct Programming Interface (DPI) Tutorial
  ☆76Updated 5 years ago
• oddball / ipxact2systemverilog
  Translates IPXACT XML to synthesizable VHDL or SystemVerilog
  ☆65Updated 2 weeks ago
• greenblat / vlsistuff
  ideas and eda software for vlsi design
  ☆51Updated this week
• merledu / caravan
  A caravan equipped with API for creating bus protocols in Chisel with ease.
  ☆14Updated 3 weeks ago
• chipsalliance / uvm-verilator
  ☆114Updated 3 months ago
• fvutils / pyhdl-if
  Python interface for cross-calling with HDL
  ☆47Updated 2 weeks ago
• hanysalah / Design-Pattern-in-SV
  This repo is created to include illustrative examples on object oriented design pattern in SV
  ☆60Updated 2 years ago
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆55Updated last year
• thomasrussellmurphy / stx_cookbook
  Altera Advanced Synthesis Cookbook 11.0
  ☆113Updated 2 years ago
• MJoergen / formal
  Playing around with Formal Verification of Verilog and VHDL
  ☆65Updated 4 years ago
• brabect1 / sta_basics_course
  Introductory course into static timing analysis (STA).
  ☆99Updated 7 months ago
• dovstamler / uvm_agents
  UVM agents
  ☆86Updated 8 years ago