isec-tugraz / coco-almaLinks
CocoAlma is an execution-aware tool for formal verification of masked implementations
☆24Updated last year
Alternatives and similar repositories for coco-alma
Users that are interested in coco-alma are comparing it to the libraries listed below
Sorting:
- Hardware Formal Verification☆17Updated 5 years ago
- A fork of Yosys that integrates the CellIFT pass☆13Updated 6 months ago
- A concolic testing engine for RISC-V embedded software with support for SystemC peripherals☆27Updated 2 years ago
- ☆14Updated 5 years ago
- The SpinalHDL design of the Proteus core, an extensible RISC-V core.☆61Updated last month
- Testing processors with Random Instruction Generation☆55Updated 3 weeks ago
- Supplemental technology files for ASAP7 PDK with Synopsys design flow☆22Updated 3 years ago
- Java library for parsing and manipulating graph representations of gate-level Verilog netlists☆15Updated 9 years ago
- Side-channel analysis setup for OpenTitan☆37Updated 3 months ago
- Integer Multiplier Generator for Verilog☆23Updated 7 months ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆98Updated last year
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…☆68Updated 3 years ago
- SCARV: a side-channel hardened RISC-V platform☆22Updated 4 years ago
- YosysHQ SVA AXI Properties☆44Updated 3 years ago
- HW Design Collateral for Caliptra RoT IP☆127Updated this week
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated 4 months ago
- A Modular Open-Source Hardware Fuzzing Framework☆36Updated 4 years ago
- This repository is compilation of basics of System Verilog Assertions in context of formal verification☆24Updated 6 years ago
- SCARV: a side-channel hardened RISC-V platform☆28Updated 3 years ago
- SystemVerilog & Verilog Module I/O parser and printer☆25Updated 4 years ago
- ☆17Updated 2 years ago
- ☆24Updated 5 years ago
- Methodology that leverages FPV to automatically discover covert channels in hardware that is time-shared between processes. AutoCC operat…☆22Updated last year
- Generator of arithmetic circuits (multipliers, adders) and approximate circuits☆39Updated 5 months ago
- A tool for synthesizing Verilog programs☆109Updated 5 months ago
- CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.☆36Updated last year
- A Modeling and Verification Platform for SoCs using ILAs☆81Updated last year
- ILA Model Database☆24Updated 5 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆34Updated 2 months ago
- ANSI-C benchmarks generated from Verilog RTL circuits with safety assertions. Used for Formal Property Verification.☆17Updated 7 years ago