isec-tugraz / coco-almaLinks
CocoAlma is an execution-aware tool for formal verification of masked implementations
☆22Updated 11 months ago
Alternatives and similar repositories for coco-alma
Users that are interested in coco-alma are comparing it to the libraries listed below
Sorting:
- Hardware Formal Verification☆15Updated 5 years ago
- A concolic testing engine for RISC-V embedded software with support for SystemC peripherals☆25Updated last year
- HW Design Collateral for Caliptra RoT IP☆110Updated this week
- Microarchitectural control flow integrity (𝜇CFI) verification checks whether there exists a control or data flow from instruction's ope…☆14Updated 2 months ago
- SCARV: a side-channel hardened RISC-V platform☆27Updated 2 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆88Updated last year
- Testing processors with Random Instruction Generation☆45Updated last month
- Integer Multiplier Generator for Verilog☆23Updated last month
- The SpinalHDL design of the Proteus core, an extensible RISC-V core.☆55Updated last month
- Fuzzing for SpinalHDL☆16Updated 2 years ago
- ☆13Updated 4 years ago
- Methodology that leverages FPV to automatically discover covert channels in hardware that is time-shared between processes. AutoCC operat…☆19Updated 10 months ago
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…☆65Updated 2 years ago
- This repository is compilation of basics of System Verilog Assertions in context of formal verification☆24Updated 6 years ago
- IOPMP IP☆19Updated last month
- ☆23Updated 4 years ago
- Side-channel analysis setup for OpenTitan☆35Updated last month
- YosysHQ SVA AXI Properties☆42Updated 2 years ago
- SCARV: a side-channel hardened RISC-V platform☆20Updated 4 years ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆39Updated 2 weeks ago
- Supplemental technology files for ASAP7 PDK with Synopsys design flow☆17Updated 2 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆30Updated 2 months ago
- SystemVerilog & Verilog Module I/O parser and printer☆25Updated 4 years ago
- A Modeling and Verification Platform for SoCs using ILAs☆77Updated last year
- ☆10Updated 3 years ago
- A Modular Open-Source Hardware Fuzzing Framework☆34Updated 3 years ago
- CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.☆32Updated last year
- pulp_soc is the core building component of PULP based SoCs☆80Updated 5 months ago
- Equivalence checking with Yosys☆45Updated 2 weeks ago
- A tool for synthesizing Verilog programs☆98Updated this week