Alternatives and similar repositories for tiny5:

Users that are interested in tiny5 are comparing it to the libraries listed below

• Wren6991 / ChristmasSoC
  Dual-core RISC-V SoC with JTAG, atomics, SDRAM
  ☆23Updated 3 years ago
• himanshu5-prog / vortexGPU
  ☆19Updated 3 years ago
• OpenPOWERFoundation / a2o
  The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, …
  ☆45Updated 9 months ago
• ToNi3141 / Rasterix
  OpenGL 1.x implementation for FPGAs
  ☆74Updated this week
• hedgeberg / UART2NAND
  Interface for exposing raw NAND i/o over UART to enable pc-side modification.
  ☆20Updated 7 years ago
• freecores / rtc
  No description
  ☆9Updated 10 years ago
• pulp-platform / clint
  RISC-V Core Local Interrupt Controller (CLINT)
  ☆25Updated last year
• hedgeberg / GlitchHammer
  A custom coprocessor and SoC for hardware security experiments in electronics.
  ☆12Updated 7 years ago
• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
  ☆29Updated this week
• PS-FPGA / ps-fpga
  The PS-FPGA project (top level)
  ☆23Updated 3 years ago
• j-core / jcore-cpu
  J-Core J2/J32 5 stage pipeline CPU core
  ☆50Updated 4 years ago
• VoidMercy / Lattice-ECP5-Bitstream-Decompiler
  Bitstream to Verilog decompiler for Lattice FPGA ECP5 chip.
  ☆20Updated 3 years ago
• semify-eda / waveform-generator
  Waveform Generator
  ☆11Updated 2 years ago
• zephray / RISu064
  Dual-issue RV64IM processor for fun & learning
  ☆57Updated last year
• embecosm / riscv-gdbserver
  GDB Server for interacting with RISC-V models, boards and FPGAs
  ☆21Updated 5 years ago
• lowRISC / muntjac
  64-bit multicore Linux-capable RISC-V processor
  ☆84Updated 5 months ago
• lioncash / biscuit
  A runtime code generator for RISC-V
  ☆42Updated last week
• OpenPOWERFoundation / a2i
  The A2I core was used as the general purpose processor for BlueGene/Q, the successor to BlueGene/L and BlueGene/P supercomputers
  ☆42Updated 2 years ago
• nand2mario / ddr3-tang-primer-20k
  DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.
  ☆50Updated last year
• ChrisPVille / jtaglet
  Easy-to-use JTAG TAP and Debug Controller core written in Verilog
  ☆25Updated 6 years ago
• lioncash / DolphinPPCTests
  PPC instruction tests
  ☆11Updated last year
• ekiwi / fst-reader
  Native Rust implementation of the FST waveform format from GTKWave.
  ☆12Updated 3 weeks ago
• SonalPinto / kronos
  Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations
  ☆70Updated last year
• pulp-platform / pulp-runtime
  Simple runtime for Pulp platforms
  ☆40Updated this week
• NukaCola-Quantum / MBIST-verilog
  A Flyweight MBIST Block - FPGA synthesizable, Multi-algorithm integrated
  ☆18Updated 6 years ago
• freecores / amber
  Amber ARM-compatible core
  ☆11Updated 10 years ago
• shengwenliang / fpga-nvme-controller
  Chisel NVMe controller
  ☆15Updated 2 years ago
• merlinepedra25 / Xilinx-Unprotect
  ☆39Updated 2 years ago
• aniketnk / circular-queue-verilog
  Implementation of a circular queue in hardware using verilog.
  ☆16Updated 5 years ago