Ashwin-Rajesh / RiSC-16Links
RiSC 16 is a simple 16 bit instruction set with 8 instructions and 3 instruction formats. This is an RTL implementation in verilog, instruction set simulator and a random instruction generator in system verilog and a rudimetary assembler in python
☆12Updated 3 years ago
Alternatives and similar repositories for RiSC-16
Users that are interested in RiSC-16 are comparing it to the libraries listed below
Sorting:
- A small and simple rv32i core written in Verilog☆15Updated 3 years ago
- Dual-core RISC-V SoC with JTAG, atomics, SDRAM☆25Updated 3 years ago
- Implementation of a circular queue in hardware using verilog.☆17Updated 6 years ago
- DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.☆61Updated 2 years ago
- RV32I single cycle simulation on open-source software Logisim.☆20Updated 3 years ago
- 5-stage RISC-V CPU, originally developed for RISCBoy☆33Updated 2 years ago
- Submission template for TT02☆25Updated 2 years ago
- Reusable Verilog 2005 components for FPGA designs☆48Updated 8 months ago
- VGA-compatible text mode functionality☆17Updated 5 years ago
- 🔌 CPU86 - Free VHDL CPU8088 IP core - ported to Papilio and Max1000 FPGA☆45Updated 2 months ago
- Example Verilog code for Ulx3s☆42Updated 3 years ago
- Basic OpenGL 1.x implementation for small FPGAs (like iCE40UP5K)☆39Updated 3 years ago
- NES FPGA implementation synthesized for the ulx3s ecp5 based fpga board☆38Updated 3 years ago
- IEEE 754 single precision floating point library in systemverilog and vhdl☆38Updated 10 months ago
- A Risc-V SoC for Tiny Tapeout☆43Updated last month
- SpinalHDL USB system for the ULPI based Arrow DECA board☆20Updated 3 years ago
- Exploring gate level simulation☆58Updated 6 months ago
- ☆14Updated 3 years ago
- A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set☆65Updated 5 months ago
- J-Core J2/J32 5 stage pipeline CPU core☆54Updated 4 years ago
- A blinky project for the ULX3S v3.0.3 FPGA board☆17Updated 6 years ago
- Mini CPU design with JTAG UART support☆20Updated 4 years ago
- Using VexRiscv without installing Scala☆39Updated 3 years ago
- Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations☆75Updated 2 years ago
- The A2I core was used as the general purpose processor for BlueGene/Q, the successor to BlueGene/L and BlueGene/P supercomputers☆47Updated 3 years ago
- ☆53Updated 3 years ago
- A SoC for DOOM☆19Updated 4 years ago
- Easy-to-use JTAG TAP and Debug Controller core written in Verilog☆33Updated 6 years ago
- Build a RISC-V computer system on fpga iCE40HX8K-EVB and run UNIX xv6 using only FOSS (free and open source hard- and software).☆56Updated 2 years ago
- ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.☆34Updated this week