Ashwin-Rajesh / RiSC-16

RiSC 16 is a simple 16 bit instruction set with 8 instructions and 3 instruction formats. This is an RTL implementation in verilog, instruction set simulator and a random instruction generator in system verilog and a rudimetary assembler in python
10Updated 2 years ago

Related projects

Alternatives and complementary repositories for RiSC-16