Ashwin-Rajesh / RiSC-16Links
RiSC 16 is a simple 16 bit instruction set with 8 instructions and 3 instruction formats. This is an RTL implementation in verilog, instruction set simulator and a random instruction generator in system verilog and a rudimetary assembler in python
☆12Updated 3 years ago
Alternatives and similar repositories for RiSC-16
Users that are interested in RiSC-16 are comparing it to the libraries listed below
Sorting:
- A small and simple rv32i core written in Verilog☆13Updated 3 years ago
- RV32I single cycle simulation on open-source software Logisim.☆20Updated 2 years ago
- DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.☆59Updated 2 years ago
- Dual-core RISC-V SoC with JTAG, atomics, SDRAM☆25Updated 3 years ago
- Build a RISC-V computer system on fpga iCE40HX8K-EVB and run UNIX xv6 using only FOSS (free and open source hard- and software).☆53Updated 2 years ago
- Implementation of a RISC-V CPU in Verilog.☆17Updated 5 months ago
- Implementation of a circular queue in hardware using verilog.☆17Updated 6 years ago
- 5-stage RISC-V CPU, originally developed for RISCBoy☆32Updated 2 years ago
- J-Core J2/J32 5 stage pipeline CPU core☆53Updated 4 years ago
- Reusable Verilog 2005 components for FPGA designs☆46Updated 6 months ago
- Tools for FPGA development.☆48Updated 3 weeks ago
- Example Verilog code for Ulx3s☆41Updated 3 years ago
- 🔌 CPU86 - Free VHDL CPU8088 IP core - ported to Papilio and Max1000 FPGA☆45Updated last week
- ☆14Updated 3 years ago
- VGA-compatible text mode functionality☆17Updated 5 years ago
- Basic OpenGL 1.x implementation for small FPGAs (like iCE40UP5K)☆39Updated 3 years ago
- Fully featured implementation of Inter-IC (I2C) bus master for FPGAs☆29Updated 5 years ago
- A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set☆62Updated 3 months ago
- iCE40HX8K development board with SRAM and bus for fast ADC, DAC, IOs☆38Updated 9 months ago
- The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, …☆49Updated 3 months ago
- A simple risc-v CPU /GPU running on an Arty A7-100T FPGA board☆30Updated 4 years ago
- ☆53Updated 3 years ago
- Submission template for TT02☆25Updated 2 years ago
- Custom 64-bit pipelined RISC processor☆18Updated last year
- Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations☆75Updated 2 years ago
- ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.☆34Updated this week
- Another size-optimized RISC-V CPU for your consideration.☆58Updated 2 weeks ago
- Exploring gate level simulation☆58Updated 4 months ago
- FPGA based microcomputer sandbox for software and RTL experimentation☆66Updated last week
- Scripts to automate building linux images for my emulator riscv_em☆15Updated last year