Ashwin-Rajesh / RiSC-16Links
RiSC 16 is a simple 16 bit instruction set with 8 instructions and 3 instruction formats. This is an RTL implementation in verilog, instruction set simulator and a random instruction generator in system verilog and a rudimetary assembler in python
☆12Updated 3 years ago
Alternatives and similar repositories for RiSC-16
Users that are interested in RiSC-16 are comparing it to the libraries listed below
Sorting:
- A small and simple rv32i core written in Verilog☆13Updated 2 years ago
- RV32I single cycle simulation on open-source software Logisim.☆19Updated 2 years ago
- DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.☆55Updated last year
- Dual-core RISC-V SoC with JTAG, atomics, SDRAM☆25Updated 3 years ago
- Example Verilog code for Ulx3s☆40Updated 3 years ago
- This repository contains the Simple As Possible Floating Point Unit design based on the IEEE-754 Standard.☆18Updated 2 years ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- ☆35Updated 6 months ago
- Implementation of a circular queue in hardware using verilog.☆17Updated 6 years ago
- Reusable Verilog 2005 components for FPGA designs☆43Updated 3 months ago
- SoftCPU/SoC engine-V☆54Updated 2 months ago
- Fusesoc compatible rtl cores☆15Updated 2 years ago
- Wishbone interconnect utilities☆41Updated 3 months ago
- Implementation of a RISC-V CPU in Verilog.☆14Updated 3 months ago
- Fully featured implementation of Inter-IC (I2C) bus master for FPGAs☆27Updated 5 years ago
- VGA-compatible text mode functionality☆17Updated 5 years ago
- A simple 8 bit UART implementation in Verilog, with tests and timing diagrams☆30Updated 2 years ago
- Use ECP5 JTAG port to interact with user design☆28Updated 3 years ago
- Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations☆73Updated 2 years ago
- A simple risc-v CPU /GPU running on an Arty A7-100T FPGA board☆29Updated 3 years ago
- Easy-to-use JTAG TAP and Debug Controller core written in Verilog☆28Updated 6 years ago
- SDRAM controller optimized to a memory bandwidth of 316MB/s☆27Updated 3 years ago
- RISC-V RV32E core designed for minimal area☆16Updated 6 months ago
- Build a RISC-V computer system on fpga iCE40HX8K-EVB and run UNIX xv6 using only FOSS (free and open source hard- and software).☆50Updated 2 years ago
- Mini CPU design with JTAG UART support☆20Updated 3 years ago
- Quickly update a bitstream with new RAM contents☆15Updated 3 years ago
- Basic OpenGL 1.x implementation for small FPGAs (like iCE40UP5K)☆37Updated 3 years ago
- IEEE 754 single precision floating point library in systemverilog and vhdl☆29Updated 5 months ago
- ☆14Updated 2 months ago
- ☆13Updated 3 years ago