Alternatives and similar repositories for RiSC-16

Users that are interested in RiSC-16 are comparing it to the libraries listed below

• rolandbernard / kleine-riscv
  A small and simple rv32i core written in Verilog
  ☆14Updated 3 years ago
• aniketnk / circular-queue-verilog
  Implementation of a circular queue in hardware using verilog.
  ☆17Updated 6 years ago
• hdl-util / vga-text-mode
  VGA-compatible text mode functionality
  ☆17Updated 5 years ago
• Wren6991 / Hazard5
  5-stage RISC-V CPU, originally developed for RISCBoy
  ☆32Updated 2 years ago
• ToNi3141 / RasteriCEr
  Basic OpenGL 1.x implementation for small FPGAs (like iCE40UP5K)
  ☆39Updated 3 years ago
• Wren6991 / libfpga
  Reusable Verilog 2005 components for FPGA designs
  ☆46Updated 7 months ago
• j-core / jcore-cpu
  J-Core J2/J32 5 stage pipeline CPU core
  ☆54Updated 4 years ago
• zeeshanrafique23 / RV32I-Logisim
  RV32I single cycle simulation on open-source software Logisim.
  ☆20Updated 3 years ago
• nand2mario / ddr3-tang-primer-20k
  DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.
  ☆59Updated 2 years ago
• ChrisPVille / jtaglet
  Easy-to-use JTAG TAP and Debug Controller core written in Verilog
  ☆33Updated 6 years ago
• nsauzede / cpu86
  🔌 CPU86 - Free VHDL CPU8088 IP core - ported to Papilio and Max1000 FPGA
  ☆45Updated last month
• projf / fpgatools
  Tools for FPGA development.
  ☆48Updated 2 months ago
• x653 / xv6-riscv-fpga
  Build a RISC-V computer system on fpga iCE40HX8K-EVB and run UNIX xv6 using only FOSS (free and open source hard- and software).
  ☆54Updated 2 years ago
• hdl-util / i2c
  Fully featured implementation of Inter-IC (I2C) bus master for FPGAs
  ☆29Updated 5 years ago
• lmEshoo / sp-i586
  soft processor core compatible with i586 instruction set(Intel Pentium) developped on Nexys4 board boots linux kernel with a ramdisk cont…
  ☆33Updated 8 years ago
• AngeloJacobo / ULX3S_FPGA_Camera_Streaming
  Verilog design files and Icestudio file for streaming the OV7670 camera using ULX3S FPGA Board
  ☆23Updated 3 years ago
• mrisc32 / mrisc32-a1
  A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA
  ☆24Updated 2 years ago
• Wren6991 / ChristmasSoC
  Dual-core RISC-V SoC with JTAG, atomics, SDRAM
  ☆25Updated 3 years ago
• enthusi / lz4_rv32i_decode
  LZ4 decoder in assembly for RiscV RV32IC
  ☆11Updated 3 years ago
• PS-FPGA / ps-fpga
  The PS-FPGA project (top level)
  ☆25Updated 4 years ago
• fredrequin / fpga_1943
  Verilog re-implementation of the famous CAPCOM arcade game
  ☆29Updated 6 years ago
• ZipCPU / zbasic
  A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
  ☆44Updated 2 years ago
• lawrie / ulx3s_examples
  Example Verilog code for Ulx3s
  ☆41Updated 3 years ago
• Arlet / verilog-65C02-microcode
  65C02 microprocessor in verilog, small size,reduced cycle count, asynchronous interface
  ☆73Updated 2 years ago
• tinyfpga / TinyFPGA-SoC
  Opensource building blocks for TinyFPGA microcontrollers and retro computers.
  ☆17Updated 8 years ago
• tongchen126 / Boot-Debian-On-Litex-Rocket
  ☆14Updated 3 years ago
• OpenPOWERFoundation / a2i
  The A2I core was used as the general purpose processor for BlueGene/Q, the successor to BlueGene/L and BlueGene/P supercomputers
  ☆45Updated 3 years ago
• lxp32 / lxp32-cpu
  A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
  ☆63Updated 4 months ago
• sylefeb / Silixel
  Exploring gate level simulation
  ☆58Updated 5 months ago
• defparam / PCI2Nano-RTL
  An open source FPGA PCI core & 8250-Compatible PCI UART core
  ☆43Updated 4 years ago