Ashwin-Rajesh / RiSC-16
RiSC 16 is a simple 16 bit instruction set with 8 instructions and 3 instruction formats. This is an RTL implementation in verilog, instruction set simulator and a random instruction generator in system verilog and a rudimetary assembler in python
☆11Updated 2 years ago
Alternatives and similar repositories for RiSC-16:
Users that are interested in RiSC-16 are comparing it to the libraries listed below
- A small and simple rv32i core written in Verilog☆13Updated 2 years ago
- RV32I single cycle simulation on open-source software Logisim.☆17Updated 2 years ago
- Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations☆70Updated last year
- DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.☆50Updated last year
- Verilog design files and Icestudio file for streaming the OV7670 camera using ULX3S FPGA Board☆20Updated 3 years ago
- Example Verilog code for Ulx3s☆40Updated 2 years ago
- FPGA based microcomputer sandbox for software and RTL experimentation☆49Updated last week
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆43Updated last year
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆74Updated this week
- J-Core J2/J32 5 stage pipeline CPU core☆50Updated 4 years ago
- Another tiny RISC-V implementation☆54Updated 3 years ago
- Reusable Verilog 2005 components for FPGA designs☆39Updated last year
- A simple 8 bit UART implementation in Verilog, with tests and timing diagrams☆25Updated last year
- A customized RISCV core made using verilog☆19Updated 3 years ago
- Dual-core RISC-V SoC with JTAG, atomics, SDRAM☆23Updated 3 years ago
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆58Updated 6 years ago
- Basic OpenGL 1.x implementation for small FPGAs (like iCE40UP5K)☆36Updated 3 years ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆76Updated last year
- Wishbone interconnect utilities☆38Updated 7 months ago
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆48Updated this week
- Quickly update a bitstream with new RAM contents☆15Updated 3 years ago
- This repository contains the Simple As Possible Floating Point Unit design based on the IEEE-754 Standard.☆18Updated last year
- ☆32Updated 2 months ago
- Tools for FPGA development.☆44Updated last year
- Quite OK Image FPGA Encoder and Decoder☆16Updated last year
- A complete HDMI transmitter implementation in VHDL☆20Updated last week
- Easy-to-use JTAG TAP and Debug Controller core written in Verilog☆23Updated 6 years ago
- An open source FPGA PCI core & 8250-Compatible PCI UART core☆40Updated 4 years ago
- Using VexRiscv without installing Scala☆37Updated 3 years ago
- Implementation of a circular queue in hardware using verilog.☆16Updated 5 years ago