Ashwin-Rajesh / RiSC-16Links
RiSC 16 is a simple 16 bit instruction set with 8 instructions and 3 instruction formats. This is an RTL implementation in verilog, instruction set simulator and a random instruction generator in system verilog and a rudimetary assembler in python
☆12Updated 3 years ago
Alternatives and similar repositories for RiSC-16
Users that are interested in RiSC-16 are comparing it to the libraries listed below
Sorting:
- A small and simple rv32i core written in Verilog☆13Updated 2 years ago
- Implementation of a circular queue in hardware using verilog.☆17Updated 6 years ago
- Dual-core RISC-V SoC with JTAG, atomics, SDRAM☆25Updated 3 years ago
- Build a RISC-V computer system on fpga iCE40HX8K-EVB and run UNIX xv6 using only FOSS (free and open source hard- and software).☆53Updated 2 years ago
- DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.☆55Updated last year
- 🔌 CPU86 - Free VHDL CPU8088 IP core - ported to Papilio and Max1000 FPGA☆44Updated 6 months ago
- ☆53Updated 2 years ago
- Reusable Verilog 2005 components for FPGA designs☆45Updated 4 months ago
- RV32I single cycle simulation on open-source software Logisim.☆20Updated 2 years ago
- The A2I core was used as the general purpose processor for BlueGene/Q, the successor to BlueGene/L and BlueGene/P supercomputers☆44Updated 2 years ago
- A SoC for DOOM☆18Updated 4 years ago
- This repository contains the Simple As Possible Floating Point Unit design based on the IEEE-754 Standard.☆18Updated 2 years ago
- Optimized RISC-V FP emulation for 32-bit processors☆34Updated 4 years ago
- Implementation of a RISC-V CPU in Verilog.☆17Updated 4 months ago
- J-Core J2/J32 5 stage pipeline CPU core☆53Updated 4 years ago
- VGA-compatible text mode functionality☆17Updated 5 years ago
- An open source FPGA PCI core & 8250-Compatible PCI UART core☆42Updated 4 years ago
- ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.☆34Updated this week
- S3GA: a simple scalable serial FPGA☆10Updated 2 years ago
- Verilog re-implementation of the famous CAPCOM arcade game☆29Updated 6 years ago
- SoftCPU/SoC engine-V☆54Updated 4 months ago
- The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, …☆48Updated 2 months ago
- A bit-serial CPU☆19Updated 5 years ago
- Basic OpenGL 1.x implementation for small FPGAs (like iCE40UP5K)☆39Updated 3 years ago
- Quite OK Image FPGA Encoder and Decoder☆20Updated 2 years ago
- RISC-V RV32E core designed for minimal area☆16Updated 8 months ago
- 65C02 microprocessor in verilog, small size,reduced cycle count, asynchronous interface☆73Updated 2 years ago
- Basic Verilog Ethernet core and C driver functions☆11Updated last month
- A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set☆61Updated last month
- soft processor core compatible with i586 instruction set(Intel Pentium) developped on Nexys4 board boots linux kernel with a ramdisk cont…☆32Updated 8 years ago