Python iterface for Cadence LEF/DEF parser.
☆41Oct 31, 2023Updated 2 years ago
Alternatives and similar repositories for lefdef-python
Users that are interested in lefdef-python are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- iccad contest 2022 problem B☆17Sep 4, 2022Updated 4 years ago
- SMT-based-STDCELL-Layout-Generator☆20Sep 30, 2021Updated 5 years ago
- ☆22Nov 29, 2022Updated 3 years ago
- Library for VLSI CAD Design Useful parsers and solvers' api are implemented.☆199May 19, 2025Updated last year
- Source code for LEF/DEF☆11Oct 16, 2018Updated 7 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- OpenROAD's Chatbot Assistant☆48Updated this week
- Cell Layout Generation for DTCO/STCO Exploration Toolkit☆34May 24, 2025Updated last year
- Public executable files and test cases of ATSim3D [ISEDA24] and ATSim3.5D [ISEDA25]☆12May 17, 2026Updated 4 months ago
- liberty parser (For parsing IC timing lib file)☆66Jul 24, 2023Updated 3 years ago
- Library Exchange Format (LEF) and Design Exchange Format (DEF)☆28Aug 13, 2020Updated 6 years ago
- ☆13Jul 3, 2020Updated 6 years ago
- Open Source Cell Library for Predictive CNFET Technology☆17Mar 12, 2026Updated 6 months ago
- A LEF/DEF Utility.☆34Aug 15, 2019Updated 7 years ago
- Power grid analysis☆23Aug 5, 2020Updated 6 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Official implementation of paper "Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluation".☆167Sep 15, 2026Updated 3 weeks ago
- ☆67Mar 8, 2021Updated 5 years ago
- ☆43May 8, 2025Updated last year
- EDA wiki☆55Mar 1, 2023Updated 3 years ago
- ☆14Jan 3, 2018Updated 8 years ago
- Cell layout generation (MH Multiheight) for DTCO/STCO exploration toolkit.☆16Oct 6, 2025Updated last year
- GDSII File Parsing, IC Layout Analysis, and Parameter Extraction☆137Apr 23, 2023Updated 3 years ago
- Mirror of the Si2 LEF/DEF parser (v5.8)☆23Sep 15, 2026Updated 3 weeks ago
- Simple strutured VERILOG netlist to SPICE netlist translator☆26Jul 31, 2026Updated 2 months ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Parser for LEF library files☆41Sep 22, 2020Updated 6 years ago
- A verified Implementation of a mini prolog☆17Nov 27, 2022Updated 3 years ago
- An OASIS and GDS2 (chip layout format) binary dump tool for debugging☆47Dec 5, 2017Updated 8 years ago
- A RISC-V RV32 model ready for SMT program synthesis.☆12Jun 23, 2021Updated 5 years ago
- Steiner Shallow-Light Tree for VLSI Routing☆65Jul 11, 2024Updated 2 years ago
- ☆16Jun 30, 2024Updated 2 years ago
- ☆58Jan 3, 2024Updated 2 years ago
- ISPD26 Contest: Post-Placement Buffering and Sizing☆35May 3, 2026Updated 5 months ago
- ☆102Jun 24, 2025Updated last year
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Courseworks of CS6165 VLSI Physical Design Automation, NTHU.☆50Jan 23, 2021Updated 5 years ago
- ChatEDA: A Large Language Model Powered Autonomous Agent for EDA (TCAD'24, NAACL'25)☆61May 21, 2025Updated last year
- An open-source EDA infrastructure and tools from netlist to GDS☆550Jul 9, 2026Updated 3 months ago
- A python library for ngspice☆15Apr 13, 2026Updated 5 months ago
- LAYout with Gridded Objects☆35Jun 18, 2020Updated 6 years ago
- ☆25May 8, 2025Updated last year
- These benchmarks were used as a part of the ICCAD23 Contest Problem C ML for static IR drop prediction☆19Feb 22, 2024Updated 2 years ago