Alternatives and similar repositories for DEF-Viewer

Users that are interested in DEF-Viewer are comparing it to the libraries listed below

• The-OpenROAD-Project / OpenRCX
  ☆22Updated 4 years ago
• jimwang99 / parser-for-chip-design
  A set of Python based parsers for multiple file format used in IC chip design, including Verilog, SPICE, lib (Synopsys Liberty).
  ☆33Updated 10 years ago
• mikaeloduh / gds2ascii-tool-project
  GDS to ASCII Converter
  ☆21Updated last week
• Coloquinte / Coloquinte_placement
  An analytical VLSI placer
  ☆28Updated 3 years ago
• sgherbst / msdsl
  Automatic generation of real number models from analog circuits
  ☆41Updated last year
• The-OpenROAD-Project / asap7_pdk_r1p7
  ☆19Updated 11 months ago
• patrickschulz / openPCells
  Parametric layout generator for digital, analog and mixed-signal integrated circuits
  ☆55Updated last week
• UNSAMDCI / PDK_ONC5
  Educational Design Kit for Synopsys Tools with a set of Characterized Standard Cell Library
  ☆33Updated 3 years ago
• idea-fasoc / fasoc
  ☆55Updated last year
• ucb-art / laygo
  LAYout with Gridded Objects
  ☆29Updated 5 years ago
• yellekelyk / PyVerilog
  Python-based Verilog Parser (currently Netlist only)
  ☆54Updated 8 years ago
• mgraczyk / coursera-vlsicad
  Programming assignments for Coursera's U of I VLSI CAD: Logic to Layout
  ☆12Updated 11 years ago
• ucdrstdenis / cdsAsync
  cdsAsync: An Asynchronous QDI VLSI Toolset & Schematic Library
  ☆25Updated 5 years ago
• andrsmllr / magic_vlsi_examples
  Some simple examples for the Magic VLSI physical chip layout tool.
  ☆30Updated 4 years ago
• unnir / CadenceSKILL-Python
  Inter Process Communication (IPC) between Python and Cadence Virtuoso
  ☆78Updated 8 years ago
• sgherbst / sky130-hello-world
  Minimal SKY130 example with self-checking LVS, DRC, and PEX
  ☆23Updated 4 years ago
• yathAg / openroad_vsd_7nmContest
  ☆15Updated 2 years ago
• curtisma / VirtuosoToolboxMatlab
  MATLAB toolbox for interfacing with the Cadence Virtuoso IC Design System
  ☆30Updated 8 years ago
• asyncvlsi / AMC
  AMC: Asynchronous Memory Compiler
  ☆49Updated 5 years ago
• bluecheetah / bag
  BAG framework
  ☆41Updated 11 months ago
• byuccl / spydrnet
  A flexible framework for analyzing and transforming FPGA netlists. Official repository.
  ☆95Updated 4 months ago
• EECS150 / asic_labs_fa21
  ☆24Updated 3 years ago
• sanggido / OpenDP
  Open Source Detailed Placement engine
  ☆38Updated 5 years ago
• ALIGN-analoglayout / AnalogDetailedRouter
  Intel's Analog Detailed Router
  ☆39Updated 5 years ago
• clin99 / awesome-eda
  ☆92Updated 6 years ago
• mabrains / sky130_klayout_pdk
  Skywater 130nm Klayout Device Generators PDK
  ☆31Updated 11 months ago
• google / bigspicy
  ☆41Updated 2 years ago
• ahmed-agiza / EDAViewer
  EDAV: Open-Source EDA Viewer; render design LEF/DEF files in your browser!
  ☆72Updated 2 years ago
• sgherbst / anasymod
  A framework for FPGA emulation of mixed-signal systems
  ☆36Updated 3 years ago
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆70Updated last month