Aperture-Electronic / Realtime-Bicubic-16X-SuperResolution-IP
APV21B - Real-time Video 16X Bicubic Super-resolution IP, AXI4-Stream Video Interface Compatible, 4K 60FPS
☆23Updated last year
Alternatives and similar repositories for Realtime-Bicubic-16X-SuperResolution-IP:
Users that are interested in Realtime-Bicubic-16X-SuperResolution-IP are comparing it to the libraries listed below
- Bitmap Processing Library & AXI-Stream Video Image VIP☆30Updated 2 years ago
- AHB DMA 32 / 64 bits☆52Updated 10 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆36Updated 2 years ago
- ☆35Updated 9 years ago
- HW JPEG decoder wrapper with AXI-4 DMA☆33Updated 4 years ago
- An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器☆43Updated 6 months ago
- ☆38Updated 2 years ago
- Bilinear interpolation realizes image scaling based on FPGA☆24Updated 4 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆33Updated 2 years ago
- A 32 point radix-2 FFT module written in Verilog☆21Updated 4 years ago
- 基于FPGA的三速以太网UDP协议栈设计☆22Updated 10 months ago
- ☆16Updated 2 years ago
- ☆9Updated 4 years ago
- AXI Interconnect☆47Updated 3 years ago
- RTL code of some arbitration algorithm☆13Updated 5 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆31Updated 2 years ago
- Verilog Code for a JPEG Decoder☆33Updated 6 years ago
- SPI interface connect to APB BUS with Verilog HDL☆25Updated 3 years ago
- An FPGA-based QOI image compressor and decompressor in Verilog. 基于FPGA的QOI图像压缩器和解压器。☆20Updated 4 months ago
- ☆23Updated 3 years ago
- 视频旋转(2019FPGA大赛)☆31Updated 4 years ago
- UART -> AXI Bridge☆60Updated 3 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆18Updated 5 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆28Updated 3 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆41Updated 8 months ago
- 128KB AXI cache (32-bit in, 256-bit out)☆47Updated 3 years ago
- DMA core compatible with AHB3-Lite☆10Updated 5 years ago
- ITMO SystemC & Verilog assignments - AMBA AHB and SPI☆21Updated 7 years ago
- ☆27Updated 5 years ago