Alternatives and similar repositories for Realtime-Bicubic-16X-SuperResolution-IP:

Users that are interested in Realtime-Bicubic-16X-SuperResolution-IP are comparing it to the libraries listed below

• Aperture-Electronic / SystemVerilog-Bitmap-Library-AXI-Image-VIP
  Bitmap Processing Library & AXI-Stream Video Image VIP
  ☆30Updated 2 years ago
• ultraembedded / core_jpeg_decoder
  HW JPEG decoder wrapper with AXI-4 DMA
  ☆34Updated 4 years ago
• WangXuan95 / FPGA-QOI
  An FPGA-based QOI image compressor and decompressor in Verilog. 基于FPGA的QOI图像压缩器和解压器。
  ☆22Updated 5 months ago
• Reconfigurable-Computing / Xilinx-FPGA-PCIe-XDMA-Tutorial
  Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核
  ☆22Updated 2 years ago
• WangXuan95 / FPGA-HDMI
  An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器
  ☆46Updated 7 months ago
• ultraembedded / core_spiflash
  SPI-Flash XIP Interface (Verilog)
  ☆36Updated 3 years ago
• ganyunhan / DUAL-OV5640-for-GOWIN
  A dual-camera based on OminiVison 5460 for GoWin GW2A-55K Combat Board
  ☆33Updated 3 years ago
• WayneGong / Image_Rotate
  视频旋转（2019FPGA大赛）
  ☆32Updated 4 years ago
• freecores / dma_ahb
  AHB DMA 32 / 64 bits
  ☆53Updated 10 years ago
• lewiz-support / LMAC_CORE3
  Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps
  ☆41Updated last year
• Lianghao-Yuan / AHB_Bus_Matrix
  ☆36Updated 9 years ago
• TheMozg / spi-amba-simulation
  ITMO SystemC & Verilog assignments - AMBA AHB and SPI
  ☆21Updated 7 years ago
• BigPig-Bro / Cyclone-IV
  【例程】简单的FPGA入门项目 适用于各类Cyclone 开发板
  ☆20Updated 2 months ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆62Updated 4 years ago
• thuCGRA / SpinalHDL_Chinese_Doc
  Translated SpinalHDL-Doc(v1.7.2) into Chinese
  ☆48Updated last year
• KasuganoSoraaa / simple-AXI2AHB-bridge
  AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc
  ☆36Updated 2 years ago
• Angelic47 / GowinDDR3_AXI4_SpinalHDL
  Gowin DDR3 Controller with AXI4 Implementation | 高云DDR3内存控制器AXI4接口实现
  ☆21Updated last year
• 0xArt / RGMII_Ethernet_Transceiver_Verilog
  Verilog module to transmit/receive to/from RGMII compatible ethernet PHY
  ☆22Updated 2 years ago
• JoseIuri / axi4lite2uart
  This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.
  ☆17Updated 6 years ago
• Nitcloud / Image_sim
  基于FPGA的图像处理模块（出自于crazybingo）（将部分IP换为纯Verilog用于跨平台移植）
  ☆45Updated 4 years ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆60Updated 3 years ago
• seonskim / verilog_axi-interconnect
  AXI Interconnect
  ☆47Updated 3 years ago
• aquaxis / aq_mipi_csi2rx_ultrascaleplus
  ☆28Updated 5 years ago
• hizbi-github / AXI4_Master_Interconnect_Slave
  A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…
  ☆31Updated 2 years ago
• echoPinkApple / bilinear
  Bilinear interpolation realizes image scaling based on FPGA
  ☆23Updated 4 years ago
• LCAI-TIHU / HW
  LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…
  ☆36Updated 2 years ago
• Frogwells / fpga_cmos_design
  这是使用FPGA开发CMOS的两个真实项目，之前的fpga_design仅是一个未完善的版本，同时也删除了一些与项目无关的东西
  ☆33Updated 7 years ago
• brown9804 / PCIe_physical_layer
  Implementation of the PCIe physical layer
  ☆33Updated last month
• funannoka / SoC-Design-DDR3-Controller
  DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
  ☆30Updated 6 years ago
• suisuisi / FPGAandUSB3.0
  FPGA和USB3.0桥片实现USB3.0通信
  ☆61Updated 3 years ago