A project demonstrate how to config ad9361 to TX mode
☆11Dec 9, 2018Updated 7 years ago
Alternatives and similar repositories for AD9361_TX_1MHz_Baseband_800Hz_IF
Users that are interested in AD9361_TX_1MHz_Baseband_800Hz_IF are comparing it to the libraries listed below
Sorting:
- My code repositry for common use.☆23Dec 31, 2021Updated 4 years ago
- A project demonstrate how to config ad9361 to TX mode and how to transmit MSK☆62May 18, 2019Updated 6 years ago
- Repository containing the DSP gateware cores☆14Feb 6, 2026Updated last month
- A project demonstrate how to config ad9361 to TX mode and how to transmit GMSK☆16Dec 9, 2018Updated 7 years ago
- VHDL implementation of carrier phase recovery (CPR) techniques for coherent optical systems☆16Dec 6, 2020Updated 5 years ago
- An open-source VHDL library for FPGA design.☆32Jun 2, 2022Updated 3 years ago
- IEEE 802.16 OFDM-based transceiver system☆28Jul 21, 2019Updated 6 years ago
- ☆35Dec 10, 2023Updated 2 years ago
- This is the verilog code for the various FPGA in the OpenHPSDR Radios☆27Mar 1, 2025Updated last year
- ☆11Sep 14, 2025Updated 5 months ago
- Open IP in Hardware Description Language.☆30Sep 4, 2023Updated 2 years ago
- ☆32Jan 23, 2021Updated 5 years ago
- Hardware Assisted IEEE 1588 IP Core☆30Jul 17, 2014Updated 11 years ago
- An AXI DDR3 SDRAM controller for FPGA☆44Dec 30, 2023Updated 2 years ago
- Fractional interpolation using a Farrow structure☆10Oct 11, 2023Updated 2 years ago
- GMSK调制和解调matlab代码☆15Apr 22, 2023Updated 2 years ago
- Baseband Receiver IP for GPS like DSSS signals☆40May 19, 2020Updated 5 years ago
- A VHDL IP for ECC (Elliptic Curve Cryptography) hardware acceleration☆46Nov 24, 2025Updated 3 months ago
- This project is designed to delay the output of the video stream in AXI-STREAM format.☆12Jul 14, 2024Updated last year
- Rate Splitting☆11Jun 23, 2020Updated 5 years ago
- FPGA Low latency 10GBASE-R PCS☆12May 23, 2023Updated 2 years ago
- Graph.dll deobfuscated☆16May 15, 2021Updated 4 years ago
- Decoding an ancient Indian epic containing 718 languages written entirely in a numerical script.☆20Aug 2, 2025Updated 7 months ago
- ☆10Aug 9, 2021Updated 4 years ago
- Utilities for Avalon Memory Map☆11Jul 11, 2024Updated last year
- EMVLogger is an open-source tool for testing and analyzing EMV chip cards and transaction logs using a comprehensive EMV Kernel Library. …☆13Jun 15, 2024Updated last year
- A plain simulation model for Frequency Hopping☆47May 18, 2019Updated 6 years ago
- 用Verilog语言编写，实现2FSK，2PSK, 2DPSK, QPSK调制解调☆43Mar 15, 2019Updated 6 years ago
- VHDL sources for a BT.656 to axi4-stream converter☆12Mar 20, 2023Updated 2 years ago
- Trying to learn Wishbone by implementing few master/slave devices☆13Jan 7, 2019Updated 7 years ago
- My attempt to build GPS (GNSS) receiver with a little help of gnuradio☆11Jan 6, 2024Updated 2 years ago
- 东北大学软件学院数据结构与算法课程设计☆10Jan 22, 2019Updated 7 years ago
- Python tools for processing Verilog files☆10Dec 7, 2011Updated 14 years ago
- Code repository for my articles on blogs.embarcadero.com and pythongui.org.☆13Feb 6, 2025Updated last year
- Turbo coder and decoder☆12Oct 11, 2023Updated 2 years ago
- Altium design files for WISP 6, including the basic sensor node and add-on boards☆13Apr 12, 2023Updated 2 years ago
- Designing and implementing LZ4 decompression algorithm in hardware (FPGA) using Verilog hardware description language☆17Feb 20, 2019Updated 7 years ago
- wifi☆12Jun 13, 2017Updated 8 years ago
- MBD FOC control using a SMO observer based on microchip model.☆10Apr 28, 2023Updated 2 years ago