Grootzz / AD9361_TX_1MHz_Baseband_800Hz_IFLinks
A project demonstrate how to config ad9361 to TX mode
☆11Updated 6 years ago
Alternatives and similar repositories for AD9361_TX_1MHz_Baseband_800Hz_IF
Users that are interested in AD9361_TX_1MHz_Baseband_800Hz_IF are comparing it to the libraries listed below
Sorting:
- My code repositry for common use.☆23Updated 3 years ago
- VHDL implementation of carrier phase recovery (CPR) techniques for coherent optical systems☆15Updated 4 years ago
- 通过SPI协议实现FPGA multiboot在线升级功能☆11Updated 7 years ago
- A collection of Opal Kelly provided design resources☆17Updated 2 weeks ago
- IEEE 802.16 OFDM-based transceiver system☆26Updated 6 years ago
- 利用ZYNQ7020实现SAR数据采集系统,其中包含硬件设计代码、上位机、测试程序。☆12Updated 6 months ago
- ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)☆12Updated 7 years ago
- The implementation of AD9371 on KC705☆21Updated 2 months ago
- FPGA Additive White Gaussian Noise Generator Using the Box Mueller Method☆10Updated 8 years ago
- Verilog modules for software-defined radio.☆18Updated 12 years ago
- Testbenches for HDL projects☆20Updated last week
- SPI to I2C Protocol Conversion Using Verilog. Final Year BTech project. Also published an IEEE paper.☆11Updated 4 years ago
- Repository containing the DSP gateware cores☆13Updated last week
- Verilog实现OFDM基带☆44Updated 9 years ago
- UART to AXI Stream interface written in VHDL☆16Updated 2 years ago
- AES implementation in MATLAB☆12Updated 8 years ago
- development interface mil-std-1553b for system on chip☆22Updated 7 years ago
- Verilog IP Cores & Tests☆13Updated 7 years ago
- DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8☆15Updated 3 years ago
- 用Verilog语言编写,实现2FSK,2PSK, 2DPSK, QPSK调制解调☆41Updated 6 years ago
- IEEE 802.11 OFDM-based transceiver system☆35Updated 7 years ago
- This project is designed to delay the output of the video stream in AXI-STREAM format.☆11Updated last year
- Partial Verilog implimentation of a WiMAX OFDM Phy☆19Updated 13 years ago
- A configuration controller solution allowing a Zynq device to configure downstream FPGAs☆14Updated 9 years ago
- ☆18Updated 4 years ago
- OscillatorIMP ecosystem FPGA IP sources☆28Updated last month
- Low Density Parity Check Decoder☆16Updated 8 years ago
- Code for paper entitled "Low Cost FPGA based Implementation of a DRFM System"☆30Updated 3 years ago
- Dual-Mode PSK Transceiver on SDR With FPGA☆40Updated 10 months ago
- VHDL functional blocks with their simulations and test sequences☆20Updated last week