lauchinyuan / Asymmetric_async_FIFOLinks
asynchronous FIFO that support Non-symmetric aspect ratios(different read and write data widths), First-Word Fall-Through and data counter.
☆26Updated 2 years ago
Alternatives and similar repositories for Asymmetric_async_FIFO
Users that are interested in Asymmetric_async_FIFO are comparing it to the libraries listed below
Sorting:
- ☆28Updated 6 months ago
- PCIE 5.0 Graduation project (Verification Team)☆97Updated last year
- FFT implement by verilog_测试验证已通过☆60Updated 9 years ago
- AXI总线连接器☆105Updated 5 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆42Updated 3 years ago
- SPI interface connect to APB BUS with Verilog HDL☆39Updated 4 years ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆134Updated 4 years ago
- Must-have verilog systemverilog modules☆37Updated 3 years ago
- ☆74Updated 10 years ago
- verilog☆21Updated 2 years ago
- AXI DMA 32 / 64 bits☆123Updated 11 years ago
- Bitmap Processing Library & AXI-Stream Video Image VIP☆35Updated 3 years ago
- ARM中通过APB总线连接的UART模块☆70Updated 5 years ago
- An uvm verification env for ahb2apb bridge☆58Updated 4 years ago
- AXI Interconnect☆54Updated 4 years ago
- 视频旋转(2019FPGA大赛)☆37Updated 5 years ago
- Final Project for my course in Advanced Verification with SystemVerilog OOP☆22Updated 4 years ago
- Pipeline FFT Implementation in Verilog HDL☆155Updated 6 years ago
- practice configure AHB-Lite bus protocol☆19Updated 6 years ago
- Open IP in Hardware Description Language.☆28Updated 2 years ago
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆63Updated 3 years ago
- ☆75Updated 4 years ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆72Updated 3 years ago
- AMBA bus generator including AXI, AHB, and APB☆118Updated 4 years ago
- Implementation of the PCIe physical layer☆60Updated 6 months ago
- ☆80Updated 3 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆39Updated 8 years ago
- ☆20Updated 3 years ago
- DDR2 memory controller written in Verilog☆78Updated 13 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆74Updated last year