lauchinyuan / Asymmetric_async_FIFO
asynchronous FIFO that support Non-symmetric aspect ratios(different read and write data widths), First-Word Fall-Through and data counter.
☆17Updated last year
Alternatives and similar repositories for Asymmetric_async_FIFO:
Users that are interested in Asymmetric_async_FIFO are comparing it to the libraries listed below
- FFT implement by verilog_测试验证已通过☆55Updated 8 years ago
- The RTL desings for the AMBA APB3 Master and Generic Slave ( Memory Interface-able )☆14Updated 2 years ago
- ☆36Updated 9 years ago
- verilog☆21Updated last year
- ☆30Updated 5 years ago
- Step by step tutorial for building CortexM0 SoC☆37Updated 3 years ago
- Must-have verilog systemverilog modules☆33Updated 2 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆36Updated 8 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆39Updated 3 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆35Updated 3 years ago
- 视频旋转(2019FPGA大赛)☆33Updated 4 years ago
- PCIE 5.0 Graduation project (Verification Team)☆68Updated last year
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆20Updated 6 years ago
- Interface Protocol in Verilog☆49Updated 5 years ago
- Generic AXI to AHB bridge☆16Updated 10 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆61Updated 8 months ago
- ☆67Updated 3 years ago
- ARM中通过APB总线连接的UART模块☆64Updated 5 years ago
- AXI总线连接器☆97Updated 5 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆16Updated 10 years ago
- I2C Master and Slave☆33Updated 9 years ago
- fpga i2c slave verilog hdl rtl☆13Updated 9 years ago
- Bitmap Processing Library & AXI-Stream Video Image VIP☆30Updated 3 years ago
- AXI Interconnect☆47Updated 3 years ago
- practice configure AHB-Lite bus protocol☆12Updated 6 years ago
- AHB DMA 32 / 64 bits☆54Updated 10 years ago
- FPGA 同步FIFO与异步FIFO☆30Updated 6 years ago
- APB to I2C☆40Updated 10 years ago
- An AXI DDR3 SDRAM controller for FPGA☆34Updated last year
- 帮助大家进行FPGA的入门,分享FPGA相关的优秀文章,优秀项目☆34Updated 3 years ago