Alternatives and similar repositories for hdl:

Users that are interested in hdl are comparing it to the libraries listed below

• chiggs / oc_jpegencode
  Fork of OpenCores jpegencode with Cocotb testbench
  ☆44Updated 9 years ago
• stevenbell / csirx
  Open-source CSI-2 receiver for Xilinx UltraScale parts
  ☆37Updated 5 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆60Updated 2 years ago
• Architech-Silica / Designing-a-Custom-AXI-Master-using-BFMs
  A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models
  ☆34Updated 7 years ago
• qermit / WishboneAXI
  Wishbone to AXI bridge (VHDL)
  ☆41Updated 5 years ago
• Architech-Silica / Designing-a-Custom-AXI-Slave-Peripheral
  A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
  ☆40Updated 6 years ago
• Elphel / eddr3
  mirror of https://git.elphel.com/Elphel/eddr3
  ☆40Updated 7 years ago
• hellgate202 / csi2_rx
  MIPI CSI-2 RX
  ☆31Updated 3 years ago
• magro732 / OpenRIO
  Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.
  ☆33Updated 7 years ago
• hdl-util / mipi-csi-2
  Capture images/video from a Raspberry Pi Camera (MIPI CSI-2) with an FPGA
  ☆68Updated 4 years ago
• CospanDesign / vivado-ip-cores
  IP Cores that can be used within Vivado
  ☆25Updated 3 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆41Updated 3 months ago
• fpga-soc / mil-std-1553b-soc
  development interface mil-std-1553b for system on chip
  ☆21Updated 7 years ago
• Elphel / x393_sata
  mirror of https://git.elphel.com/Elphel/x393_sata
  ☆33Updated 4 years ago
• sbourdeauducq / serdes-tdc
  SERDES-based TDC core for Spartan-6
  ☆18Updated 12 years ago
• SanjayRai / PCIE_AXI_BRIDGE
  Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices
  ☆29Updated 9 years ago
• ericgineer / CIC
  A CIC filter implemented in Verilog
  ☆22Updated 9 years ago
• TI-Bonn / vercolib_pcie
  VHDL PCIe Transceiver
  ☆28Updated 4 years ago
• delhatch / Zynq_UDP
  Transfer data over UDP with a Zedboard. This is an example project that transmits and receives data over UDP.
  ☆25Updated 4 years ago
• AnttiLukats / HackaZynq
  Open Source ZYNQ Board
  ☆31Updated 9 years ago
• SpinalHDL / VexRiscvSoftcoreContest2018
  ☆63Updated 6 years ago
• ZipCPU / videozip
  A ZipCPU SoC for the Nexys Video board supporting video functionality
  ☆17Updated 5 months ago
• Cognoscan / AxiCores
  AXI4-Compatible Verilog Cores, along with some helper modules.
  ☆16Updated 5 years ago
• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆42Updated 2 weeks ago
• suoto / fpga_cores
  ☆33Updated 2 years ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆49Updated last year
• VideoGPU / FMC_MIPI
  FMC card to allow interfacing Xilinx FPGA boards with Jetson TX2 or TX1 via CSI-2 camera interface
  ☆17Updated 2 years ago
• BBN-Q / VHDL-JESD204b
  JESD204b modules in VHDL
  ☆30Updated 6 years ago
• gtaylormb / ultra96v2_imx219_to_displayport
  Raspberry Pi v2 camera (IMX219) to DisplayPort of Ultra96-V2 board through PL
  ☆69Updated 3 years ago
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆20Updated 2 years ago