An LLVM based mini-C to Verilog High-level Synthesis tool
☆41Mar 7, 2025Updated last year
Alternatives and similar repositories for c-ll-verilog
Users that are interested in c-ll-verilog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Synthesiser for Asynchronous Verilog Language☆20Oct 29, 2014Updated 11 years ago
- Hi-DMM: High-Performance Dynamic Memory Management in HLS (High-Level Synthesis)☆25Oct 30, 2018Updated 7 years ago
- ☆10Oct 15, 2021Updated 4 years ago
- Python version of tools to work with AIG formatted files☆12May 20, 2025Updated 11 months ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆101Mar 29, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Convert C files into Verilog☆22Jan 27, 2019Updated 7 years ago
- Hardware Formal Verification☆17Aug 10, 2020Updated 5 years ago
- ☆18Nov 9, 2022Updated 3 years ago
- a fast fixed size block allocator☆20Aug 29, 2015Updated 10 years ago
- Random Generator of Btor2 Files☆10Sep 2, 2023Updated 2 years ago
- A Formal Verification Framework for Chisel☆19Apr 9, 2024Updated 2 years ago
- ☆18Jul 12, 2024Updated last year
- SPICE based IBIS simulation☆18Jan 2, 2025Updated last year
- ICCAD'23 Best Paper Award candidate: Robust GNN-based Representation Learning for HLS☆25May 23, 2024Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Logic Synthesis System from UC Berkeley (Unofficial Distribution)☆15Jun 4, 2019Updated 6 years ago
- MachSMT: An ML-Driven Algorithm Selection tool for SMT Solvers☆26Apr 21, 2023Updated 3 years ago
- An Extensible Framework for Hardware Verification and Debugging☆17Sep 14, 2022Updated 3 years ago
- Arithmetic multiplier benchmarks☆12Nov 13, 2017Updated 8 years ago
- Python Verilog-AMS Parser☆12Oct 13, 2015Updated 10 years ago
- ANSI-C benchmarks generated from Verilog RTL circuits with safety assertions. Used for Formal Property Verification.☆17Dec 1, 2018Updated 7 years ago
- Integer Multiplier Generator for Verilog☆25Jul 4, 2025Updated 10 months ago
- ☆64Jul 21, 2020Updated 5 years ago
- A simple dot file / graph generator for Verilog syntax trees.☆23Jul 16, 2016Updated 9 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Official Repository for the ICLR 2022 paper "Generalization of Neural Combinatorial Solvers through the Lens of Adversarial Robustness"☆13Nov 20, 2022Updated 3 years ago
- RISC-V Formal in Chisel☆13Apr 9, 2024Updated 2 years ago
- Qingnang Smart Diagnosis is an end-to-end AI healthcare framework with field-proven application capabilities, designed to provide efficie…☆19Apr 30, 2026Updated 2 weeks ago
- ☆15Sep 14, 2020Updated 5 years ago
- IronMan+alpha: Graph Neural Network and Reinforcement Learning in High-Level Synthesis☆27Jun 24, 2022Updated 3 years ago
- propositional satisfiability problem (SAT) goes neural and deep☆12Aug 17, 2021Updated 4 years ago
- Research project from UCI's AICPS lab: using GNNs to enable hardware security and prevent hardware trojans☆10Mar 31, 2021Updated 5 years ago
- ☆15Feb 6, 2021Updated 5 years ago
- Script to generate Carl Bugeja styled PCB motors for KiCad with Python☆17Jul 18, 2023Updated 2 years ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- Official repository for paper "Goal-Aware Neural SAT Solver"☆17Jun 10, 2023Updated 2 years ago
- easter egg is a flexible, high-performance e-graph library with support of multiple additional assumptions at once☆13Mar 27, 2025Updated last year
- A copy of the latest version of MVSIS☆13Apr 18, 2021Updated 5 years ago
- Yamaha DX7 synthesizer with JAX☆20Jan 23, 2026Updated 3 months ago
- Gate-Level Simulation on a GPU☆10Nov 22, 2016Updated 9 years ago
- Information about verification tools. Browse the data at https://slebok.github.io/proverb/☆33Dec 9, 2023Updated 2 years ago
- QuteRTL: A RTL Front-End Towards Intelligent Synthesis and Verification☆16Nov 8, 2016Updated 9 years ago