sabbaghm / c-ll-verilog
An LLVM based mini-C to Verilog High-level Synthesis tool
☆35Updated last month
Alternatives and similar repositories for c-ll-verilog:
Users that are interested in c-ll-verilog are comparing it to the libraries listed below
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Updated 4 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆21Updated last week
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 5 years ago
- Benchmarks for Yosys development☆24Updated 5 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- A C to verilog compiler☆52Updated 9 years ago
- Demo SoC for SiliconCompiler.☆59Updated last month
- Mirror of tachyon-da cvc Verilog simulator☆42Updated last year
- A fault-injection framework using Chisel and FIRRTL☆35Updated 2 years ago
- Useful utilities for BAR projects☆31Updated last year
- ☆55Updated 2 years ago
- SCARV: a side-channel hardened RISC-V platform☆26Updated 2 years ago
- An open-source custom cache generator.☆33Updated last year
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 4 years ago
- The PE for the second generation CGRA (garnet).☆17Updated this week
- HeteroSim is a full system simulator supporting x86 multicore processors combined with a FPGA via bus-based architecture. Flexible design…☆21Updated 8 years ago
- RISC-V GPGPU☆34Updated 5 years ago
- A Verilog Synthesis Regression Test☆37Updated last year
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆36Updated 4 years ago
- ☆15Updated 4 years ago
- Naive Educational RISC-V -- A simple single-stage RV32I processor☆27Updated 4 years ago
- A library and command-line tool for querying a Verilog netlist.☆26Updated 2 years ago
- Simple MIDAS Examples☆12Updated 6 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆49Updated 9 years ago
- Open Source AES☆31Updated last year
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆65Updated 2 months ago
- ☆102Updated 2 years ago
- The Shang high-level synthesis framework☆119Updated 10 years ago
- ☆22Updated 7 years ago
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆103Updated 5 months ago