sabbaghm / c-ll-verilogLinks
An LLVM based mini-C to Verilog High-level Synthesis tool
☆39Updated 8 months ago
Alternatives and similar repositories for c-ll-verilog
Users that are interested in c-ll-verilog are comparing it to the libraries listed below
Sorting:
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 5 years ago
- C++17 implementation of an AST for Verilog code generation☆24Updated 2 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆49Updated 10 years ago
- Demo SoC for SiliconCompiler.☆62Updated last week
- ☆15Updated 4 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Updated 5 years ago
- ☆104Updated 3 years ago
- ☆56Updated 3 years ago
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆116Updated 5 months ago
- Synthesiser for Asynchronous Verilog Language☆20Updated 11 years ago
- The PE for the second generation CGRA (garnet).☆17Updated 6 months ago
- HeteroSim is a full system simulator supporting x86 multicore processors combined with a FPGA via bus-based architecture. Flexible design…☆21Updated 9 years ago
- FPGA Assembly (FASM) Parser and Generator☆97Updated 3 years ago
- RTLCheck☆22Updated 7 years ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆37Updated 4 years ago
- SCARV: a side-channel hardened RISC-V platform☆27Updated 2 years ago
- A Verilog Synthesis Regression Test☆37Updated last year
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 3 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- Tutorial for integrating PyMTL and Vivado HLS☆19Updated 9 years ago
- Collection of test cases for Yosys☆17Updated 3 years ago
- ☆32Updated 2 years ago
- Quasar 2.0: Chisel equivalent of SweRV-EL2☆31Updated 4 years ago
- The Shang high-level synthesis framework☆120Updated 11 years ago
- FPGA tool performance profiling☆102Updated last year
- SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research☆38Updated last year
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…☆66Updated 2 years ago
- An open source high level synthesis (HLS) tool built on top of LLVM☆125Updated last year
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆148Updated last week
- Naive Educational RISC-V -- A simple single-stage RV32I processor☆27Updated 5 years ago