sabbaghm / c-ll-verilog
An LLVM based mini-C to Verilog High-level Synthesis tool
☆35Updated this week
Alternatives and similar repositories for c-ll-verilog:
Users that are interested in c-ll-verilog are comparing it to the libraries listed below
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 4 years ago
- Benchmarks for Yosys development☆23Updated 5 years ago
- The PE for the second generation CGRA (garnet).☆17Updated last week
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆21Updated last week
- A library and command-line tool for querying a Verilog netlist.☆26Updated 2 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆52Updated 4 years ago
- An open-source custom cache generator.☆30Updated 11 months ago
- HeteroSim is a full system simulator supporting x86 multicore processors combined with a FPGA via bus-based architecture. Flexible design…☆21Updated 8 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆63Updated last month
- A collection of big designs to run post-synthesis simulations with yosys☆49Updated 9 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 5 years ago
- C++17 implementation of an AST for Verilog code generation☆24Updated last year
- A fault-injection framework using Chisel and FIRRTL☆34Updated 2 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- SCARV: a side-channel hardened RISC-V platform☆24Updated 2 years ago
- Mutation Cover with Yosys (MCY)☆80Updated this week
- ☆55Updated 2 years ago
- A low-level intermediate representation for hardware description languages☆28Updated 4 years ago
- Collection of test cases for Yosys☆18Updated 3 years ago
- ☆102Updated 2 years ago
- SoftCPU/SoC engine-V☆54Updated last year
- The specification for the FIRRTL language☆51Updated this week
- A Verilog Synthesis Regression Test☆37Updated 11 months ago
- Python interface to FPGA interchange format☆41Updated 2 years ago
- Floating point modules for CHISEL☆31Updated 10 years ago
- A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga☆26Updated 5 years ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆38Updated 3 months ago
- ☆33Updated 2 years ago
- Xilinx Unisim Library in Verilog☆75Updated 4 years ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆27Updated 5 years ago