FlorentCLMichel / karatsuba_multiplication_verilogLinks
A simple implementation of the Karatsuba multiplication algorithm
☆11Updated 9 months ago
Alternatives and similar repositories for karatsuba_multiplication_verilog
Users that are interested in karatsuba_multiplication_verilog are comparing it to the libraries listed below
Sorting:
- Verilog implementation of 1024 bit Hybrid Montgomery Multiplication/Exponentiation☆12Updated 6 years ago
- Implementation of ECC on FPGA-Zynq7000 SoC☆19Updated 6 years ago
- An end-to-end chip authentication architecture based on SRAM PUF and public key cryptography.☆17Updated 6 years ago
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆41Updated 6 years ago
- Asynchronous FIFO for transferring data between two asynchronous clock domains☆17Updated 9 years ago
- RISC-V instruction set extensions for SM4 block cipher☆21Updated 5 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆55Updated 4 years ago
- a 2048 bit RSA verilog project basing on Montgomery , Karatsuba multiplier☆25Updated 3 years ago
- An FPGA Implementation of Arbiter PUF with 4x4 Switch Blocks☆16Updated 5 years ago
- Verilog HDL implementation of Elliptic Curve Cryptography (ECC) over GF(2^163)☆22Updated 8 years ago
- SDRAM controller with AXI4 interface☆100Updated 6 years ago
- System Verilog and Emulation. Written all the five channels.☆35Updated 8 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆68Updated 5 years ago
- opensource crypto IP core☆29Updated 5 years ago
- Verilog Implementation of modular exponentiation using Montgomery multiplication☆37Updated 11 years ago
- General Purpose AXI Direct Memory Access☆62Updated last year
- Verilog for a SECDED Hsaio ECC and a DEC ECC. Power, delay, and area are compared for Berkeley MASIC EEW241B - Advanced Digital Integrate…☆51Updated 10 years ago
- FPGA implementation of Chinese SM4 encryption algorithm.☆56Updated 7 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆73Updated last year
- Elgamal's over Elliptic Curves☆19Updated 7 years ago
- This is a Verilog algorithm which takes 8bits and encrypts the data for the purpose of secure communication based on the concept of Ellip…☆32Updated 7 years ago
- few python scripts to clone all IP cores from opencores.org☆25Updated 2 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆42Updated 3 years ago
- DMA Hardware Description with Verilog☆18Updated 6 years ago
- Hardware Implementation of Advanced Encryption Standard Algorithm in Verilog☆41Updated 8 years ago
- UART -> AXI Bridge☆69Updated 4 years ago
- USB -> AXI Debug Bridge☆41Updated 4 years ago
- FPGA implementation of a cryptographically secure physical unclonable function based on learning parity with noise problem.☆15Updated 8 years ago
- AES加密解密算法的Verilog实现☆67Updated 9 years ago
- AXI Interconnect☆54Updated 4 years ago