FlorentCLMichel / karatsuba_multiplication_verilog
A simple implementation of the Karatsuba multiplication algorithm
☆11Updated last year
Alternatives and similar repositories for karatsuba_multiplication_verilog:
Users that are interested in karatsuba_multiplication_verilog are comparing it to the libraries listed below
- Verilog implementation of 1024 bit Hybrid Montgomery Multiplication/Exponentiation☆10Updated 5 years ago
- a 2048 bit RSA verilog project basing on Montgomery , Karatsuba multiplier☆19Updated 2 years ago
- Implementation of ECC on FPGA-Zynq7000 SoC☆17Updated 5 years ago
- RISC-V instruction set extensions for SM4 block cipher☆19Updated 4 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆47Updated 3 years ago
- DMA Hardware Description with Verilog☆12Updated 5 years ago
- Implementation of the PCIe physical layer☆32Updated 2 weeks ago
- A simple, scalable, source-synchronous, all-digital DDR link☆21Updated 2 months ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆36Updated 2 years ago
- Hamming ECC Encoder and Decoder to protect memories☆29Updated this week
- USB2.0 Verilog☆17Updated 5 years ago
- AXI Interconnect☆47Updated 3 years ago
- ☆16Updated 2 years ago
- FPGA 同步FIFO与异步FIFO☆29Updated 5 years ago
- Verilog Code for a JPEG Decoder☆33Updated 6 years ago
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆36Updated 5 years ago
- USB -> AXI Debug Bridge☆35Updated 3 years ago
- FPGA和USB3.0桥片实现USB3.0通信☆57Updated 3 years ago
- System Verilog and Emulation. Written all the five channels.☆32Updated 7 years ago
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆48Updated 5 months ago
- ☆9Updated 4 years ago
- Verilog HDL implementation of Elliptic Curve Cryptography (ECC) over GF(2^163)☆18Updated 7 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆61Updated 4 years ago
- zqh_riscv is an open source SOC system based on riscv core and tilelink NOC bus. coding with PHGL language(python DSL language). this pro…☆34Updated 3 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆31Updated 2 years ago
- UART -> AXI Bridge☆60Updated 3 years ago
- PCI Express controller model☆47Updated 2 years ago
- General Purpose AXI Direct Memory Access☆48Updated 8 months ago
- ☆16Updated 5 years ago
- The memory model was leveraged from micron.☆22Updated 6 years ago