FlorentCLMichel / karatsuba_multiplication_verilog

Related projects ⓘ

Alternatives and complementary repositories for karatsuba_multiplication_verilog

• p4r4xor / Montgomery1024
  Verilog implementation of 1024 bit Hybrid Montgomery Multiplication/Exponentiation
  ☆10Updated 4 years ago
• ultraembedded / core_axi_cache
  128KB AXI cache (32-bit in, 256-bit out)
  ☆44Updated 3 years ago
• funannoka / SoC-Design-DDR3-Controller
  DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
  ☆29Updated 6 years ago
• raymondrc / riscv-isa-extension-for-SM4
  RISC-V instruction set extensions for SM4 block cipher
  ☆18Updated 4 years ago
• yvnr4you / AMBA_AXI3
  System Verilog and Emulation. Written all the five channels.
  ☆32Updated 7 years ago
• loghall / axi_cache
  verification of simple axi-based cache
  ☆17Updated 5 years ago
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆28Updated last month
• abdelrhman-oun / DDR5_PHY_WriteOperation
  ☆33Updated 2 years ago
• alice820621 / SystemVerilog-Implementation-of-DDR3-Controller
  The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…
  ☆21Updated 6 years ago
• akhan3 / async-fifo
  Asynchronous FIFO for transferring data between two asynchronous clock domains
  ☆16Updated 8 years ago
• crypt-xie / XCryptCore
  Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)
  ☆35Updated 4 years ago
• shiva-t / Elliptical-Curve-Cryptography-FPGA
  Implementation of ECC on FPGA-Zynq7000 SoC
  ☆17Updated 5 years ago
• wanderingnail / AXI_DMA
  ☆16Updated last year
• StanfordAHA / AhaM3SoC
  SoC Based on ARM Cortex-M3
  ☆25Updated 5 months ago
• ultraembedded / core_usb_bridge
  USB -> AXI Debug Bridge
  ☆35Updated 3 years ago
• 2cc2ic / DMA-S2MM-and-MM2S
  Build an open source, extremely simple DMA.
  ☆19Updated 5 years ago
• ahmad2smile / SHA256_Verilog
  Verilog based FPGA Design of SHA256 Simulated on ModelSim
  ☆19Updated 6 years ago
• tej-chavan / Design-and-Verification-of-DDR3-Memory-Controller
  The memory model was leveraged from micron.
  ☆19Updated 6 years ago
• KasuganoSoraaa / simple-AXI2AHB-bridge
  AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc
  ☆31Updated 2 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆44Updated 6 months ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆58Updated 4 years ago
• zdszx / Modexpowering3
  a 2048 bit RSA verilog project basing on Montgomery , Karatsuba multiplier
  ☆16Updated 2 years ago
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆54Updated 4 years ago
• ecelab-org / Split-Chip_authentication
  An end-to-end chip authentication architecture based on SRAM PUF and public key cryptography.
  ☆15Updated 4 years ago
• fighter212 / ahb2apb
  this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.
  ☆15Updated 10 years ago
• Shehab-Naga / ddr5_phy
  DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision
  ☆41Updated 7 months ago
• govindjeevan / Weighted-Round-Robin-Arbiter
  Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components
  ☆18Updated 6 years ago
• fatestudio / RSA4096_NEW
  ☆12Updated 9 years ago
• brown9804 / PCIe_physical_layer
  Implementation of the PCIe physical layer
  ☆29Updated 4 years ago