AlexKly / Simple-Voice-Activity-Detector-using-MFCC-based-on-FPGA-KintexLinks
Voice Activity Detector based on MFCC features and DNN model
☆29Updated 2 years ago
Alternatives and similar repositories for Simple-Voice-Activity-Detector-using-MFCC-based-on-FPGA-Kintex
Users that are interested in Simple-Voice-Activity-Detector-using-MFCC-based-on-FPGA-Kintex are comparing it to the libraries listed below
Sorting:
- LMS sound filtering by Verilog☆43Updated 5 years ago
- ☆11Updated 5 years ago
- FFT implementation using CORDIC algorithm written in Verilog.☆34Updated 7 years ago
- This is an SoC design dedicated to Keyword Spotting (KWS) based on a neural-network accelerator and the wujian100 platform.☆54Updated 5 years ago
- EE 272B - VLSI Design Project☆13Updated 4 years ago
- AHB DMA 32 / 64 bits☆58Updated 11 years ago
- ☆20Updated 3 years ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆17Updated 2 years ago
- A 32-point pipelined Fast Fourier transform processor, using single path delay architecture, and based on radix2-DIF(decimation-in-freque…☆50Updated 6 years ago
- AHB/APB SRAM Inf, VCS&Verdi Sim.☆15Updated 3 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆42Updated 3 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆19Updated 11 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆14Updated 3 years ago
- ☆28Updated 6 months ago
- 3×3脉动阵列乘法器☆50Updated 6 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆48Updated 2 years ago
- LMS-Adaptive Filter implement using verilog and Matlab☆48Updated 9 years ago
- An AXI DDR3 SDRAM controller for FPGA☆44Updated 2 years ago
- Verilog cache implementation of 4-way FIFO 16k Cache☆20Updated 13 years ago
- Verilog and matlab implementation of tanh using Cordic algorithm☆11Updated 5 years ago
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆12Updated 2 years ago
- Hand Writing Digital Recognization Based on FPGA, we desiged a SoC embeded a Cortex M3 core and other peripherals,this SoC run a CNN. The…☆13Updated 2 years ago
- FFT implement by verilog_测试验证已通过☆60Updated 9 years ago
- configurable cordic core in verilog☆53Updated 11 years ago
- ☆26Updated 4 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆43Updated 3 years ago
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆29Updated 3 years ago
- A Direct Memory Access Controller (DMAC) with AHB-lite bus interface☆17Updated last year
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆32Updated 7 years ago
- Implementation of the PCIe physical layer☆60Updated 6 months ago