AlexKly / Simple-Voice-Activity-Detector-using-MFCC-based-on-FPGA-Kintex
Voice Activity Detector based on MFCC features and DNN model
☆19Updated last year
Alternatives and similar repositories for Simple-Voice-Activity-Detector-using-MFCC-based-on-FPGA-Kintex:
Users that are interested in Simple-Voice-Activity-Detector-using-MFCC-based-on-FPGA-Kintex are comparing it to the libraries listed below
- This is an SoC design dedicated to Keyword Spotting (KWS) based on a neural-network accelerator and the wujian100 platform.☆49Updated 4 years ago
- Verilog code for an efficient and scalable DFT calculator (using the FFT algorithm). Meant to be implemented on an Intel DE10-Lite FPGA d…☆14Updated 4 years ago
- LMS sound filtering by Verilog☆39Updated 5 years ago
- EE 272B - VLSI Design Project☆11Updated 3 years ago
- Design some simple RISV-V cores via verilog and vivado. 复旦大学《计算机与智能处理器体系结构 AI Core and RISC Architecture》Projects☆14Updated 3 years ago
- Single Long Short Term Memory (LSTM) cell : Verilog Implementation☆30Updated 4 years ago
- FFT implementation using CORDIC algorithm written in Verilog.☆31Updated 6 years ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆50Updated 7 years ago
- An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器☆52Updated 9 months ago
- Cortex M0 based SoC☆72Updated 3 years ago
- A Mel-frequency cepstrum core in FPGA☆19Updated 3 years ago
- ☆12Updated 5 years ago
- A 32-point pipelined Fast Fourier transform processor, using single path delay architecture, and based on radix2-DIF(decimation-in-freque…☆48Updated 5 years ago
- Hand Writing Digital Recognization Based on FPGA, we desiged a SoC embeded a Cortex M3 core and other peripherals,this SoC run a CNN. The…☆10Updated 2 years ago
- FIR,FFT based on Verilog☆13Updated 7 years ago
- Interface Protocol in Verilog☆49Updated 5 years ago
- SPI interface connect to APB BUS with Verilog HDL☆31Updated 3 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆30Updated 2 years ago
- RTL Verilog library for various DSP modules☆86Updated 3 years ago
- Pipeline FFT Implementation in Verilog HDL☆105Updated 6 years ago
- This is the first step to implement RNN on FPGAs. All modules are heavily commented. We will use High-Level Synthesis to turn these code …☆22Updated 5 years ago
- Hardware accelerator for convolutional neural networks☆43Updated 2 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 3 years ago
- How to Accelerate an Image Upscaling CNN on FPGA Using HLS☆24Updated 3 years ago
- AHB DMA 32 / 64 bits☆54Updated 10 years ago
- MulApprox - A comprehensive library of state-of-the-art approximate multipliers☆25Updated 3 years ago
- ☆38Updated 4 years ago
- Verilog and matlab implementation of tanh using Cordic algorithm☆9Updated 4 years ago
- LMS-Adaptive Filter implement using verilog and Matlab☆42Updated 8 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆30Updated 4 years ago