Alternatives and similar repositories for sail-arm

Users that are interested in sail-arm are comparing it to the libraries listed below

• CTSRD-CHERI / sail-cheri-riscv
  CHERI-RISC-V model written in Sail
  ☆66Updated 5 months ago
• rems-project / isla
  Symbolic execution tool for Sail ISA specifications
  ☆79Updated 3 months ago
• alastairreid / asl-interpreter
  Example implementation of Arm's Architecture Specification Language (ASL)
  ☆50Updated 3 months ago
• mit-plv / kami
  A Platform for High-Level Parametric Hardware Specification and its Modular Verification
  ☆163Updated last month
• CTSRD-CHERI / TestRIG
  Testing processors with Random Instruction Generation
  ☆50Updated last month
• rems-project / rmem
  rmem public repo
  ☆48Updated 7 months ago
• alastairreid / mra_tools
  Tools to process ARM's Machine Readable Architecture Specification
  ☆136Updated 5 years ago
• project-oak / silveroak
  Formal specification and verification of hardware, especially for security and privacy.
  ☆128Updated 3 years ago
• diffblue / hw-cbmc
  The HW-CBMC and EBMC Model Checkers for Verilog
  ☆99Updated this week
• CTSRD-CHERI / llvm-project
  Fork of LLVM adding CHERI support
  ☆60Updated last week
• TeamVoss / VossII
  The source code to the Voss II Hardware Verification Suite
  ☆56Updated 3 weeks ago
• agurfinkel / btor2mlir
  BTOR2 MLIR project
  ☆26Updated last year
• CTSRD-CHERI / qemu
  QEMU with support for CHERI
  ☆63Updated 3 weeks ago
• stanford-centaur / pono
  Pono: A flexible and extensible SMT-based model checker
  ☆117Updated 2 weeks ago
• IntelLabs / asl-interpreter
  Interpreter and compiler for the ISA specification language "Architecture Specification Language" (ASL)
  ☆25Updated 3 months ago
• pydrofoil / pydrofoil
  A fast RISC-V emulator based on the RISC-V Sail model, and an experimental ARM one
  ☆82Updated last week
• daniellustig / coatcheck
  COATCheck
  ☆13Updated 7 years ago
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆74Updated 5 years ago
• SRI-CSL / l3riscv
  An executable specification of the RISCV ISA in L3.
  ☆42Updated 6 years ago
• maerhart / llhd
  A low-level intermediate representation for hardware description languages
  ☆28Updated 5 years ago
• GaloisInc / grift
  Galois RISC-V ISA Formal Tools
  ☆61Updated 4 months ago
• CTSRD-CHERI / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆34Updated last week
• rzhang2285 / Coppelia
  Code repository for Coppelia tool
  ☆23Updated 5 years ago
• comsec-group / cascade-artifacts
  Artifacts for Cascade: CPU Fuzzing via Intricate Program Generation (USENIX Security 2024)
  ☆137Updated last year
• ymanerka / rtlcheck
  RTLCheck
  ☆23Updated 7 years ago
• ymanerka / pipeproof
  PipeProof
  ☆11Updated 6 years ago
• B-Lang-org / bsc-contrib
  A place to share libraries and utilities that don't belong in the core bsc repo
  ☆37Updated last month
• mit-plv / riscv-coq
  RISC-V Specification in Coq
  ☆116Updated 2 months ago
• daniellustig / pipecheck
  ☆19Updated 10 years ago
• draperlaboratory / VIBES
  Verified, Incremental, Binary Editing with Synthesis
  ☆54Updated 2 years ago