psychogenic / microcotbLinks
micro version of cocotb, to run on microcontrollers or desktop to get hardware in the loop
☆18Updated 11 months ago
Alternatives and similar repositories for microcotb
Users that are interested in microcotb are comparing it to the libraries listed below
Sorting:
- A current mode buck converter on the SKY130 PDK☆34Updated 4 years ago
- End-to-End Open-Source I2C GPIO Expander☆35Updated last week
- assorted library of utility cores for amaranth HDL☆102Updated last year
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆59Updated 2 months ago
- A flexible and scalable development platform for modern FPGA projects.☆39Updated this week
- sample VCD files☆41Updated last month
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆115Updated this week
- Hardware Design Tool - Mixed Signal Simulation with Verilog☆89Updated last year
- Python script to transform a VCD file to wavedrom format☆84Updated 3 years ago
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆88Updated 3 months ago
- Drawio => VHDL and Verilog☆61Updated 2 years ago
- datasheet generator☆30Updated 6 months ago
- ULPI Link Wrapper (USB Phy Interface)☆34Updated 5 years ago
- 12 bit SAR ADC for TinyTapeout 7☆14Updated last year
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆53Updated 2 years ago
- sump3 logic analyzer☆37Updated this week
- Time to Digital Converter (TDC)☆36Updated 5 years ago
- Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process☆19Updated 10 months ago
- An abstract language model of VHDL written in Python.☆60Updated last week
- Framework Open EDA Gui☆73Updated last year
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆32Updated 3 years ago
- Small footprint and configurable JESD204B core☆50Updated 3 weeks ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆47Updated this week
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆110Updated this week
- ☆20Updated 3 years ago
- An Amateur Radio Transceiver IC (2.4 / 5 / 10 GHz)☆73Updated 4 years ago
- ☆48Updated 2 years ago
- This repository contains iCEBreaker examples for Amaranth HDL.☆39Updated 2 years ago
- Nix flake for openXC7☆45Updated 10 months ago
- An example of analogue design using open source IC design tools☆29Updated 4 years ago