tommythorn / yari
YARI is a high performance open source FPGA soft-core RISC implementation, binary compatible with MIPS I. The distribution package includes a complete SoC, simulator, GDB stub, scripts, and various examples.
☆45Updated 3 months ago
Alternatives and similar repositories for yari:
Users that are interested in yari are comparing it to the libraries listed below
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Updated 2 years ago
- USB 1.1 Device IP Core☆20Updated 7 years ago
- SoftCPU/SoC engine-V☆54Updated last week
- CMod-S6 SoC☆40Updated 7 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆33Updated 8 years ago
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆43Updated 2 years ago
- Small footprint and configurable Inter-Chip communication cores☆56Updated last month
- An example OMI Device FPGA with 2 DDR4 memory ports☆16Updated 2 years ago
- shdl6800: A 6800 processor written in SpinalHDL☆26Updated 5 years ago
- LEON2 SPARC CPU IP core LGPL by Gaisler Research☆18Updated 11 years ago
- Open Processor Architecture☆26Updated 8 years ago
- IRSIM switch-level simulator for digital circuits☆32Updated 10 months ago
- LatticeMico32 soft processor☆105Updated 10 years ago
- A bit-serial CPU☆18Updated 5 years ago
- Flexible Byte transport protocol for bus bridging CPUs to FPGAs over UART,SPI,SERDES physical interfaces☆32Updated 3 months ago
- Reusable Verilog 2005 components for FPGA designs☆40Updated last month
- A simple jtag programming tool that has been verified on a variety of Xilinx Series7 platforms.☆35Updated 2 years ago
- Example Verilog code for Ulx3s☆40Updated 2 years ago
- A small 32-bit implementation of the RISC-V architecture☆32Updated 4 years ago
- 🔌 Compact JTAG ("cJTAG") to 4-wire JTAG (IEEE 1149.1) bridge.☆23Updated 3 years ago
- ☆10Updated 5 years ago
- Minimal microprocessor☆20Updated 7 years ago
- A RISC-V SBC based around the LambdaConcept USB2Sniffer FPGA board.☆29Updated 4 years ago
- OpenGL-like graphics pipeline on a Xilinx FPGA☆32Updated 14 years ago
- A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA☆24Updated last year
- A Verilog Synthesis Regression Test☆37Updated last year
- A gdbstub for connecting GDB to a RISC-V Debug Module☆27Updated 5 months ago
- IP submodules, formatted for easier CI integration☆29Updated last year
- Ethernet MAC 10/100 Mbps☆25Updated 3 years ago
- MR1 formally verified RISC-V CPU☆54Updated 6 years ago