YARI is a high performance open source FPGA soft-core RISC implementation, binary compatible with MIPS I. The distribution package includes a complete SoC, simulator, GDB stub, scripts, and various examples.
☆48Dec 4, 2024Updated last year
Alternatives and similar repositories for yari
Users that are interested in yari are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Yet Another RISC-V Implementation☆101Sep 21, 2024Updated last year
- A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set☆66May 29, 2025Updated last year
- ☆25Oct 24, 2022Updated 3 years ago
- ☆13Nov 29, 2025Updated 8 months ago
- Network components (NIC, Switch) for FireBox☆19Oct 27, 2024Updated last year
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Android USB Accessory☆15Jun 12, 2018Updated 8 years ago
- RISC-V Processor written in Amaranth HDL☆40Jan 21, 2022Updated 4 years ago
- Demo SoC☆10Oct 17, 2023Updated 2 years ago
- Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools☆127Feb 19, 2016Updated 10 years ago
- Lemberg is a time-predictable VLIW processor optimized for performance.☆21May 8, 2013Updated 13 years ago
- My second attempt at a RISC-V CPU with learnings form my previous attempt.☆11Apr 27, 2026Updated 3 months ago
- System on Chip toolkit for nMigen☆19Apr 29, 2020Updated 6 years ago
- LatticeMico32 soft processor☆105Oct 10, 2014Updated 11 years ago
- Drop In USB CDC ACM core for iCE40 FPGA☆37Sep 5, 2021Updated 4 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Analog and power building blocks for sky130 pdk☆22Mar 3, 2021Updated 5 years ago
- Dual-issue RV64IM processor for fun & learning☆64Jul 4, 2023Updated 3 years ago
- A collection of core generators to use with FuseSoC☆18Aug 23, 2024Updated last year
- RISC-V instruction set CPUs in HardCaml☆15Sep 20, 2016Updated 9 years ago
- I2S Digital Audio Components☆13May 27, 2014Updated 12 years ago
- The SparkFun RED-V Thing Plus is a low-cost, development board featuring the Freedom E310 SoC which brings with it the RISC-V instruction…☆12Dec 12, 2019Updated 6 years ago
- ☆44Jan 26, 2020Updated 6 years ago
- A computer (FPGA SoC) based on the MRISC32-A1 CPU☆53Sep 2, 2023Updated 2 years ago
- The BERI and CHERI processor and hardware platform☆51Mar 27, 2017Updated 9 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Misc documentation and specifications☆14Feb 26, 2022Updated 4 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆137Jul 11, 2025Updated last year
- Repository containing common Makefiles for setting up conda environments.☆10Feb 10, 2023Updated 3 years ago
- zip manipulation library | zip压缩解压库☆12Jul 27, 2023Updated 3 years ago
- A configurable USB 2.0 device core☆31Jun 12, 2020Updated 6 years ago
- RISC-V Debugger☆17Apr 2, 2025Updated last year
- RISC-V CPU implementation in Amaranth HDL (aka nMigen)☆34Aug 27, 2024Updated last year
- Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.☆65Nov 5, 2021Updated 4 years ago
- USB DFU bootloader gateware / firmware for FPGAs☆71Jan 30, 2026Updated 6 months ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆95Aug 10, 2018Updated 8 years ago
- My KiCAD libraries☆22Updated this week
- 集成多功能网关☆10Dec 24, 2017Updated 8 years ago
- A RISC-V assembler library for Scala/Chisel HDL projects☆16Aug 12, 2026Updated last week
- ☆15Jun 24, 2018Updated 8 years ago
- Experiments with Yosys cxxrtl backend☆50Jan 16, 2025Updated last year
- SERDES-based TDC core for Spartan-6☆19Aug 2, 2012Updated 14 years ago