The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor
☆15Apr 11, 2023Updated 3 years ago
Alternatives and similar repositories for bfu_dif_fft_rtl
Users that are interested in bfu_dif_fft_rtl are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆17Feb 9, 2023Updated 3 years ago
- UART models for cocotb☆38Aug 24, 2026Updated last month
- I2C models for cocotb☆49Aug 24, 2026Updated last month
- Error correction and detection example Verilog (hamming and Reed-Solomon) to accompany presentation material☆10Jan 14, 2024Updated 2 years ago
- AXI interface modules for Cocotb☆366Aug 24, 2026Updated last month
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- 9444 RISC-V 64IMA CPU and related tools and peripherals.☆28May 20, 2021Updated 5 years ago
- JPEG的正向离散余弦变化、量化、Z字形编码、对DC编码、AC编码、熵编码以及图像重构☆13May 27, 2019Updated 7 years ago
- Ethernet interface modules for Cocotb☆83Aug 28, 2026Updated last month
- Radix-4 1024 point fft in verilog☆12Apr 29, 2020Updated 6 years ago
- Audio filtering with pyfda and cocotb☆13Sep 24, 2020Updated 6 years ago
- An Open Source Link Protocol and Controller☆29Jul 26, 2021Updated 5 years ago
- Implementation of ECC on FPGA-Zynq7000 SoC☆21Jul 12, 2019Updated 7 years ago
- Example of an easy way to take cs notes☆11Mar 11, 2021Updated 5 years ago
- Drawio => VHDL and Verilog☆62Oct 15, 2023Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Advanced Integrated Circuits 2025☆14Nov 1, 2025Updated 11 months ago
- Dilithium is a digital signature scheme that is strongly secure under chosen message attacks based on the hardness of lattice problems ov…☆17Jul 28, 2023Updated 3 years ago
- This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…☆65Jun 30, 2026Updated 3 months ago
- Verilog HDL implementation of Elliptic Curve Cryptography (ECC) over GF(2^163)☆22Oct 31, 2017Updated 8 years ago
- RISC-V Nox core☆72Jul 22, 2025Updated last year
- Towards Real-Time Practical Image Compression with Lightweight Attention☆15Jan 5, 2026Updated 9 months ago
- A 32 point radix-2 FFT module written in Verilog☆25Jun 28, 2020Updated 6 years ago
- 使用决策树ID3，C4.5，CART分别生成随机森林(Using ID3, C4.5, CART decision trees to achieve RF)☆13Aug 21, 2020Updated 6 years ago
- ☆20Sep 16, 2022Updated 4 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆13Sep 9, 2026Updated last month
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆24Apr 15, 2021Updated 5 years ago
- ☆16Aug 15, 2021Updated 5 years ago
- A Full open-source/Full with Python/ interactive course for all who like to know "What are Communication Circuits?" from scratch to basic…☆12Jan 14, 2024Updated 2 years ago
- RV64IMAC modelling using System Verilog HDL☆28Aug 15, 2026Updated 2 months ago
- ☆16Sep 4, 2025Updated last year
- EEP 225 Electrical Machines lecture notes. Alexandria University, Spring 2022☆43Jun 11, 2022Updated 4 years ago
- A coverage library for Chisel designs☆11Mar 12, 2020Updated 6 years ago
- Python module for 8B10B encoding and decoding☆12Jul 25, 2023Updated 3 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆16Jun 7, 2022Updated 4 years ago
- Source codes and calibration scripts for clock tree synthesis☆40Feb 18, 2020Updated 6 years ago
- Multi-path UDP protocol - an example implementation☆10Jul 6, 2015Updated 11 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆18Feb 12, 2024Updated 2 years ago
- Educational verilog library that supports IEEE754 floating point arithmetic with a parametrizable mantissa and exponent☆33Mar 13, 2025Updated last year
- A hardware component library developed with ROHD.☆117Updated this week
- Examples for using pyuvm☆23Jun 5, 2024Updated 2 years ago