dvanmali / Superscalar_Pipeline_ProcessorView external linksLinks
Design consists of a 32-bit MIPS superscalar pipeline processor in functional Verilog. Runs a cache based memory system, a branch predictor, and a 2-way superscalar pipeline processor issuing two instructions at a time. Intended for creators Yiming Gan and Dylan Vanmali.
☆15Oct 9, 2017Updated 8 years ago
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