Design consists of a 32-bit MIPS superscalar pipeline processor in functional Verilog. Runs a cache based memory system, a branch predictor, and a 2-way superscalar pipeline processor issuing two instructions at a time. Intended for creators Yiming Gan and Dylan Vanmali.
☆15Oct 9, 2017Updated 8 years ago
Alternatives and similar repositories for Superscalar_Pipeline_Processor
Users that are interested in Superscalar_Pipeline_Processor are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Radix-4 1024 point fft in verilog☆12Apr 29, 2020Updated 6 years ago
- ☆24Feb 10, 2024Updated 2 years ago
- Verification IP for Watchdog☆13Apr 6, 2021Updated 5 years ago
- WM8731 Audio CODEC using Verilog (DE2-115)☆11Jul 28, 2019Updated 6 years ago
- A Verilog implementation of a pipelined MIPS processor☆11Oct 20, 2017Updated 8 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Alpha64 R10000 Two-Way Superscalar Processor☆12May 6, 2019Updated 7 years ago
- Verilog implementation of Bubble Sorter and Odd Even Transposition Sorter.☆15Nov 22, 2015Updated 10 years ago
- This project aims to implement a full SDRAM controller for Altera DE2-115 FPGA☆14Nov 24, 2014Updated 11 years ago
- Verilog implementation of a 4-way Set associative cache with a write buffer (write) policy and FIFO replacement policy☆42Oct 23, 2016Updated 9 years ago
- Modular SRAM-based indirectly-indexed 2D hierarchical-search Binary Content Addressable Memory (II-2D-BCAM)☆17Nov 10, 2024Updated last year
- A MIPS CPU with dual-issue, out-of-order, and 5-stage pipelines☆11Nov 28, 2019Updated 6 years ago
- This repository contains a SystemVerilog implementation of a parametrized Round Robin arbiter with three instantiation options☆13Jan 28, 2024Updated 2 years ago
- Modular SRAM-based 2D hierarchical-search Binary Content Addressable Memory (2D-BCAM)☆22Nov 10, 2024Updated last year
- A 32 point radix-2 FFT module written in Verilog☆25Jun 28, 2020Updated 6 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Code for paper entitled "Low Cost FPGA based Implementation of a DRFM System"☆31Dec 10, 2021Updated 4 years ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆14Nov 9, 2015Updated 10 years ago
- MIPS R3000 processor verilog code to be synthesized on Spartan 3E FPGA board.☆25Oct 3, 2018Updated 7 years ago
- ASIC Design lab. Pipelined, Cached, Multicore MIPS Processor☆11Aug 23, 2017Updated 8 years ago
- Verilog cache implementation of 4-way FIFO 16k Cache☆21Dec 8, 2012Updated 13 years ago
- Design and implementation in VHDL for FPGAs of a single cycle RISC-V based architecture☆14Jul 24, 2020Updated 6 years ago
- Modular SRAM-based indirectly-indexed 2D hierarchical-search Ternary Content Addressable Memory (II-2D-TCAM)☆23Nov 10, 2024Updated last year
- Real-Time Bluetooth Networks - UTAustinX☆28Jan 15, 2017Updated 9 years ago
- Super scalar Processor design☆21Sep 7, 2014Updated 11 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Integrating Event-based Dynamic Vision Sensors with Sparse Hyperdimensional Computing☆13Jul 9, 2020Updated 6 years ago
- Wallace and Dadda tree multiplier generator in vhdl and verilog☆14Mar 14, 2026Updated 4 months ago
- 16-Point FFT is developed in order to accurately model that of the MATLAB function. . The module successfully tested using verilog testbe…☆19May 27, 2016Updated 10 years ago
- Fast division by invariant integers using multiplication☆13Apr 11, 2026Updated 3 months ago
- Builds and parses PCIe Transport Layer Packets (TLPs)☆45Jul 21, 2022Updated 4 years ago
- This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-…☆11Jul 19, 2022Updated 4 years ago
- A multi-banked non-blocking cache that handles efficiently thousands of outstanding misses, especially suited for bandwidth-bound latency…☆22Dec 3, 2020Updated 5 years ago
- RSSI Localization using a MATLAB server to calculate path loss model from RSSI data and plot real time position of User☆24Sep 14, 2014Updated 11 years ago
- 32-bit RISC-V Emulator☆28Feb 23, 2019Updated 7 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Symbolic differentation of algebraic expressions with Python and Tcl interfaces.☆19Oct 12, 2025Updated 9 months ago
- Spectrum analyzer system using a 512-point FFT, in a Cyclone IV FPGA. Reads i2s audio from the codec and then does all FFT/VGA functions.…☆32Feb 9, 2018Updated 8 years ago
- Educational 16-bit MIPS Processor☆18Feb 16, 2019Updated 7 years ago
- Integer Multiplier Generator for Verilog☆25Jul 4, 2025Updated last year
- ☆13Sep 21, 2021Updated 4 years ago
- A Kubernetes cluster to learn Kubernetes. It includes Argo CD, Grafana, Prometheus, Loki, Tempo, Phlare and VictoriaMetrics.☆11Updated this week
- Converting systemverilog to verilog.☆10Feb 15, 2018Updated 8 years ago