Design consists of a 32-bit MIPS superscalar pipeline processor in functional Verilog. Runs a cache based memory system, a branch predictor, and a 2-way superscalar pipeline processor issuing two instructions at a time. Intended for creators Yiming Gan and Dylan Vanmali.
☆15Oct 9, 2017Updated 8 years ago
Alternatives and similar repositories for Superscalar_Pipeline_Processor
Users that are interested in Superscalar_Pipeline_Processor are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Verification IP for Watchdog☆13Apr 6, 2021Updated 5 years ago
- Alpha64 R10000 Two-Way Superscalar Processor☆12May 6, 2019Updated 6 years ago
- Verilog implementation of Bubble Sorter and Odd Even Transposition Sorter.☆15Nov 22, 2015Updated 10 years ago
- Modular SRAM-based indirectly-indexed 2D hierarchical-search Binary Content Addressable Memory (II-2D-BCAM)☆17Nov 10, 2024Updated last year
- This project aims to implement a full SDRAM controller for Altera DE2-115 FPGA☆14Nov 24, 2014Updated 11 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- A MIPS CPU with dual-issue, out-of-order, and 5-stage pipelines☆11Nov 28, 2019Updated 6 years ago
- ☆22May 13, 2025Updated 11 months ago
- Fast TLB simulator for RISC-V systems☆16May 16, 2019Updated 6 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆37Dec 30, 2022Updated 3 years ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆14Nov 9, 2015Updated 10 years ago
- SHA256 hardware accelerator, synthesized for and mapped on the Zynq core of the Zybo board by Digilent☆27Jul 10, 2018Updated 7 years ago
- Code for paper entitled "Low Cost FPGA based Implementation of a DRFM System"☆31Dec 10, 2021Updated 4 years ago
- MIPS R3000 processor verilog code to be synthesized on Spartan 3E FPGA board.☆25Oct 3, 2018Updated 7 years ago
- A 32 point radix-2 FFT module written in Verilog☆25Jun 28, 2020Updated 5 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Verilog cache implementation of 4-way FIFO 16k Cache☆20Dec 8, 2012Updated 13 years ago
- A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.☆21Apr 7, 2025Updated last year
- Modular SRAM-based indirectly-indexed 2D hierarchical-search Ternary Content Addressable Memory (II-2D-TCAM)☆23Nov 10, 2024Updated last year
- Super scalar Processor design☆21Sep 7, 2014Updated 11 years ago
- Fast division by invariant integers using multiplication☆13Apr 5, 2026Updated last week
- Fast extraction of all external links from wikipedia☆13Sep 22, 2018Updated 7 years ago
- This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-…☆11Jul 19, 2022Updated 3 years ago
- ASIC Design lab. Pipelined, Cached, Multicore MIPS Processor☆11Aug 23, 2017Updated 8 years ago
- Builds and parses PCIe Transport Layer Packets (TLPs)☆45Jul 21, 2022Updated 3 years ago
- Wordpress hosting with auto-scaling - Free Trial • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- RISC-V Superscalar Educational Simulator based on Tomasulo's Algorithm☆27Nov 1, 2025Updated 5 months ago
- Express DLA implementation for FPGA, revised based on NVDLA.☆11Oct 17, 2019Updated 6 years ago
- RSSI Localization using a MATLAB server to calculate path loss model from RSSI data and plot real time position of User☆24Sep 14, 2014Updated 11 years ago
- 32-bit RISC-V Emulator☆27Feb 23, 2019Updated 7 years ago
- Valgrind is an instrumentation framework for building dynamic analysis tools. There are Valgrind tools that can automatically detect many…☆33Feb 29, 2024Updated 2 years ago
- A multi-banked non-blocking cache that handles efficiently thousands of outstanding misses, especially suited for bandwidth-bound latency…☆21Dec 3, 2020Updated 5 years ago
- Integer Multiplier Generator for Verilog☆24Jul 4, 2025Updated 9 months ago
- Symbolic differentation of algebraic expressions with Python and Tcl interfaces.☆19Oct 12, 2025Updated 6 months ago
- Educational 16-bit MIPS Processor☆18Feb 16, 2019Updated 7 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- ☆13Sep 21, 2021Updated 4 years ago
- 16-Point FFT is developed in order to accurately model that of the MATLAB function. . The module successfully tested using verilog testbe…☆18May 27, 2016Updated 9 years ago
- A Kubernetes cluster to learn Kubernetes. It includes Argo CD, Grafana, Prometheus, Loki, Tempo, Phlare and VictoriaMetrics.☆11Apr 9, 2026Updated last week
- ☆12May 19, 2022Updated 3 years ago
- Converting systemverilog to verilog.☆10Feb 15, 2018Updated 8 years ago
- Spectrum analyzer system using a 512-point FFT, in a Cyclone IV FPGA. Reads i2s audio from the codec and then does all FFT/VGA functions.…☆31Feb 9, 2018Updated 8 years ago
- Used for hardware trojan detection（Based on Trust_Hub）☆10Jul 30, 2019Updated 6 years ago