briansune / FFT-R22SDFLinks
R22SDF FFT VLSI/FPGA investigate and implementation
☆15Updated 3 years ago
Alternatives and similar repositories for FFT-R22SDF
Users that are interested in FFT-R22SDF are comparing it to the libraries listed below
Sorting:
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆55Updated 3 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆36Updated 4 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆44Updated last year
- Must-have verilog systemverilog modules☆36Updated 3 years ago
- AXI Interconnect☆49Updated 3 years ago
- This is verification project that we are writing SystemVerilog code to verify 8/16/32 bit SDRAM Controller Which is Originally developed …☆25Updated 8 years ago
- ☆20Updated 2 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆17Updated 10 years ago
- A 32 point radix-2 FFT module written in Verilog☆23Updated 4 years ago
- A 32-point pipelined Fast Fourier transform processor, using single path delay architecture, and based on radix2-DIF(decimation-in-freque…☆49Updated 5 years ago
- ☆25Updated 4 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆21Updated 4 years ago
- Reed Solomon Encoder and Decoder Digital IP☆21Updated 5 years ago
- Interface Protocol in Verilog☆50Updated 5 years ago
- DDR3 function verification environment in UVM☆25Updated 7 years ago
- FFT implementation using CORDIC algorithm written in Verilog.☆33Updated 6 years ago
- 学习AXI接口，以及xilinx DDR3 IP使用☆37Updated 8 years ago
- Asynchronous fifo in verilog☆35Updated 9 years ago
- 异步FIFO的内部实现☆24Updated 6 years ago
- Verilog RTL Design☆40Updated 3 years ago
- Tests for the design flow with Synopsys tools for the implementation of a RISC-V processor.☆22Updated 9 months ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆38Updated 2 years ago
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆20Updated 6 years ago
- Implementation of the PCIe physical layer☆43Updated last month
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆33Updated 2 years ago
- Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…☆22Updated 6 years ago
- Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …☆14Updated 10 years ago
- AHB DMA 32 / 64 bits☆56Updated 10 years ago
- Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀☆29Updated last year
- This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…☆54Updated last year