R22SDF FFT VLSI/FPGA investigate and implementation
☆17Apr 22, 2022Updated 4 years ago
Alternatives and similar repositories for FFT-R22SDF
Users that are interested in FFT-R22SDF are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 基于FPGA的FFT☆19Feb 18, 2019Updated 7 years ago
- FFT algorithm for fpga☆26Aug 17, 2021Updated 5 years ago
- SEA-S7_gesture recognition☆17Aug 1, 2020Updated 6 years ago
- Radix-4 1024 point fft in verilog☆12Apr 29, 2020Updated 6 years ago
- Neural Network accelerator powered by MVUs and RISC-V.☆13Jul 21, 2024Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- sliding DFT for FPGA, targetting Lattice ICE40 1k☆76Apr 24, 2020Updated 6 years ago
- HDL code for a complex multiplier with AXI stream interface☆17Mar 18, 2026Updated 7 months ago
- FPGA PWM generator and motor controller modules☆12Mar 9, 2021Updated 5 years ago
- R2MDC FFT/IFFT processor adaptive to 64/128/256/512 point☆19Dec 23, 2025Updated 10 months ago
- Open area for user contributions☆13Jan 28, 2023Updated 3 years ago
- Sound synthetizer with an fpga☆11Mar 14, 2015Updated 11 years ago
- FPGA-CNN Application for fruit detection based on Logos-PGL22G Board☆14Aug 24, 2022Updated 4 years ago
- An oscilloscope written for the Mojo V3, a Spartan-6 based FPGA☆11May 23, 2017Updated 9 years ago
- CNN accelerator using NoC architecture☆18Dec 6, 2018Updated 7 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Hardware random number generator for FPGAs☆10May 7, 2015Updated 11 years ago
- A DDS core written in VHDL.☆11Jan 5, 2019Updated 7 years ago
- Tutorial on how to use the AXI ACP on the UltraZed-EG IOCC☆11Jun 13, 2018Updated 8 years ago
- Verilog module to transmit/receive to/from RGMII compatible ethernet PHY☆33Dec 31, 2022Updated 3 years ago
- 轻量级跨平台 Verilog 仿真工程管理器,支持 Node cli 和 VS Code 扩展☆16Oct 16, 2026Updated 2 weeks ago
- MurPhySDR is an open source software-defined radio platform based on the AD9364 transceiver IC.☆14Jul 9, 2024Updated 2 years ago
- Nexys 4 DDR Artix-7☆12Jun 15, 2018Updated 8 years ago
- Embedded server for MaRCoS system☆12Apr 13, 2026Updated 6 months ago
- ☆12Nov 4, 2025Updated 11 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆19Jul 29, 2014Updated 12 years ago
- fpga for utrasound mobile device☆13Aug 10, 2015Updated 11 years ago
- A GPU built from scratch which can render graphics and train ML models☆15Jul 4, 2026Updated 3 months ago
- prebuilt images of openipc groundstations☆12May 15, 2025Updated last year
- N.E.O.N. Architecture — Open source GPU RTL in Verilog. Token dataflow, hardware ray tracing, frame generation. First silicon target: 28n…☆22Jun 14, 2026Updated 4 months ago
- A custom 16-bit computer☆13Oct 17, 2018Updated 8 years ago
- ☆11Dec 28, 2018Updated 7 years ago
- digital recognition base on FPGA☆12Nov 10, 2019Updated 6 years ago
- Linux UIO Driver for AXI DMA☆15Jul 23, 2018Updated 8 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Silicon-proven INT8 systolic NPU (8×8 MAC array) taped out on SkyWater 130nm via LibreLane. Features a custom 32-bit ISA, UART–APB host i…☆20May 24, 2026Updated 5 months ago
- - Use FPGA to implement MIPI interface; - Get command from PC through USB communication; - Decode command in FPGA☆13Jul 18, 2017Updated 9 years ago
- This open-source repository aims to stitch several separate video streams into a single video using DDR3/4 storage via the AXI interface.…☆22Oct 28, 2024Updated 2 years ago
- HDL code for a complex multiplier with AXI stream Interface☆13Apr 6, 2023Updated 3 years ago
- High-performance FPGA-based JPEG codec accelerator☆13Dec 1, 2018Updated 7 years ago
- FPGA-Based USB-Input Audio Digital to Analogue Converter☆18Jun 11, 2021Updated 5 years ago
- GPU-accelerated RePlAce☆14Jun 11, 2024Updated 2 years ago