briansune / FFT-R22SDFLinks
R22SDF FFT VLSI/FPGA investigate and implementation
☆16Updated 3 years ago
Alternatives and similar repositories for FFT-R22SDF
Users that are interested in FFT-R22SDF are comparing it to the libraries listed below
Sorting:
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆56Updated 3 years ago
- AXI Interconnect☆50Updated 3 years ago
- A 32 point radix-2 FFT module written in Verilog☆23Updated 5 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆37Updated 4 years ago
- ☆56Updated 2 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆37Updated 8 years ago
- Implementation of the PCIe physical layer☆45Updated this week
- Must-have verilog systemverilog modules☆36Updated 3 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆44Updated last year
- ☆20Updated 2 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆58Updated last year
- PCIE 5.0 Graduation project (Verification Team)☆78Updated last year
- SDRAM controller with AXI4 interface☆94Updated 5 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆65Updated 11 months ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆42Updated 3 years ago
- AHB DMA 32 / 64 bits☆56Updated 11 years ago
- RTL Verilog library for various DSP modules☆90Updated 3 years ago
- General Purpose AXI Direct Memory Access☆53Updated last year
- UART -> AXI Bridge☆61Updated 4 years ago
- Interface Protocol in Verilog☆50Updated 5 years ago
- DDR2 memory controller written in Verilog☆77Updated 13 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆38Updated 2 years ago
- Designing means to communicate as an SPI master, being a part of AXI interface☆17Updated last year
- This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification☆32Updated 5 years ago
- ☆25Updated 4 years ago
- ☆46Updated 4 years ago
- Verilog RTL Design☆43Updated 3 years ago
- This is verification project that we are writing SystemVerilog code to verify 8/16/32 bit SDRAM Controller Which is Originally developed …☆25Updated 8 years ago
- APB to I2C☆42Updated 11 years ago
- FFT implement by verilog_测试验证已通过☆58Updated 8 years ago