A Claude Code plugin for process management from requirement sorting to delivery
☆21Jun 4, 2026Updated last month
Alternatives and similar repositories for fnw
Users that are interested in fnw are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- RTL agent team; Harness for Agentic hardware design and verificiation.☆39Updated this week
- "Middleware" (infrastructure) for host-FPGA applications (e.g., accelerators)☆19Sep 26, 2024Updated last year
- 基于玄铁openc906,搭建最小化SoC系统☆21Apr 7, 2025Updated last year
- ☆16Dec 4, 2021Updated 4 years ago
- I am developing a set of general-purpose shareable data structures for C# and Java all of whose fields are public readonly/final, and use…☆11Updated this week
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Official PyTorch Code for "Dynamic Temperature Knowledge Distillation"☆11Mar 28, 2025Updated last year
- Radix-4 1024 point fft in verilog☆12Apr 29, 2020Updated 6 years ago
- Automated UVM testbench generator from Verilog RTL with optional LLM integration for advanced logic creation.☆28Feb 24, 2026Updated 4 months ago
- OpenExSys_NoC a mesh-based network on chip IP.☆21Dec 1, 2023Updated 2 years ago
- Polar Decoder☆12Jan 19, 2023Updated 3 years ago
- Flute 3.1 with CMake support☆16Jul 25, 2019Updated 6 years ago
- HLS implemented systolic array structure☆41Nov 13, 2017Updated 8 years ago
- ☆11Nov 30, 2022Updated 3 years ago
- [DATE'2025, TCAD'2025] Terafly : A Multi-Node FPGA Based Accelerator Design for Efficient Cooperative Inference in LLMs☆38Nov 13, 2025Updated 8 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆19Jul 25, 2018Updated 7 years ago
- Network on Chip for MPSoC☆28Jun 16, 2026Updated 3 weeks ago
- Convert AEDAT4 files from DV into AEDAT-2.0 files for jAER☆10Feb 23, 2024Updated 2 years ago
- A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.☆15Nov 9, 2014Updated 11 years ago
- 使用verilog实现流水线 FFT☆16Jul 1, 2024Updated 2 years ago
- Some embedded knowledge, especially for interview.☆24Dec 23, 2021Updated 4 years ago
- Hardware Accelerators on FPGA for Computer Vision Applications☆14Dec 16, 2025Updated 6 months ago
- VeriFlow-CC: A Claude Code-driven RTL design pipeline. Automates Chip-on-Chat from architecture to synthesis (iVerilog/Yosys) using a sta…☆36Updated this week
- SDIO Device Verilog Core☆24Jul 25, 2018Updated 7 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Official implementation for "Knowledge Distillation with Refined Logits".☆23Aug 26, 2024Updated last year
- ☆20Mar 12, 2024Updated 2 years ago
- ☆10May 25, 2021Updated 5 years ago
- 物件導向-戴文凱☆13Jun 1, 2021Updated 5 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆35Jul 10, 2016Updated 10 years ago
- Some simple attempts at building GeNN models☆10Oct 10, 2025Updated 9 months ago
- 浙江大学课程攻略共享计划☆12Jul 23, 2021Updated 4 years ago
- Board: PYNQ-Z2, Vitis version: 2022.1☆20Sep 2, 2024Updated last year
- AI-powered SystemVerilog development assistant — design, verify, debug, and deliver working RTL with natural language.☆95May 21, 2026Updated last month
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times …☆28Jul 4, 2019Updated 7 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆32Oct 30, 2015Updated 10 years ago
- The official project website of "Small Scale Data-Free Knowledge Distillation" (SSD-KD for short, published in CVPR 2024).☆22Jun 13, 2024Updated 2 years ago
- Code for ICML 2023 paper "Quantifying the Knowledge in GNNs for Reliable Distillation into MLPs"☆22Sep 24, 2025Updated 9 months ago
- USB Type-C Power Delivery FPGA☆33Apr 24, 2026Updated 2 months ago
- ☆20Jul 14, 2025Updated last year
- Integrated Circuit Design Contest (ICDC) - 大學院校積體電路設計競賽☆25Apr 20, 2022Updated 4 years ago