A Claude Code plugin for process management from requirement sorting to delivery
☆26Jun 4, 2026Updated 2 months ago
Alternatives and similar repositories for fnw
Users that are interested in fnw are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- RTL agent team; Harness for Agentic hardware design and verificiation.☆48Updated this week
- "Middleware" (infrastructure) for host-FPGA applications (e.g., accelerators)☆20Sep 26, 2024Updated last year
- Amazon F1-inspired Xilinx VCU118 hardware design framework☆14Jan 4, 2021Updated 5 years ago
- ☆16Dec 4, 2021Updated 4 years ago
- Radix-4 1024 point fft in verilog☆12Apr 29, 2020Updated 6 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- This repository contains tutorial code and supplementary note for point cloud processing.☆12Jun 21, 2026Updated 2 months ago
- - Use FPGA to implement MIPI interface; - Get command from PC through USB communication; - Decode command in FPGA☆13Jul 18, 2017Updated 9 years ago
- Programmatically control ROS Bag files.☆13Sep 5, 2017Updated 8 years ago
- Polar Decoder☆12Jan 19, 2023Updated 3 years ago
- Official website for Jiachen Project (甲辰计划).☆66Updated this week
- ☆11Nov 30, 2022Updated 3 years ago
- 黃鐘揚老師的"系統晶片驗證"作業與專題(SoCV)☆11Jan 18, 2024Updated 2 years ago
- HLS implemented systolic array structure☆41Nov 13, 2017Updated 8 years ago
- 简洁的测试平台日志，波形(FSDB/VCD)，根因分析MCP Server. A Simple and Universal MCP Server to Debug Testbench Simulation Failures Via Log Parsing And Wave…☆62Jul 30, 2026Updated 3 weeks ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- 基于玄铁openc906，搭建最小化SoC系统☆21Apr 7, 2025Updated last year
- Network on Chip for MPSoC☆29Aug 7, 2026Updated 2 weeks ago
- Convert AEDAT4 files from DV into AEDAT-2.0 files for jAER☆10Feb 23, 2024Updated 2 years ago
- VeriFlow-CC: A Claude Code-driven RTL design pipeline. Automates Chip-on-Chat from architecture to synthesis (iVerilog/Yosys) using a sta…☆45Aug 3, 2026Updated 3 weeks ago
- A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.☆15Nov 9, 2014Updated 11 years ago
- SDIO Device Verilog Core☆25Jul 25, 2018Updated 8 years ago
- Hardware Accelerators on FPGA for Computer Vision Applications☆16Dec 16, 2025Updated 8 months ago
- SystemVerilog Development Environment☆53Sep 9, 2021Updated 4 years ago
- 使用verilog实现流水线 FFT☆16Jul 1, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- 物件導向-戴文凱☆12Jun 1, 2021Updated 5 years ago
- Some simple attempts at building GeNN models☆10Oct 10, 2025Updated 10 months ago
- A Fast Pythonic Simulator for Neuromorphic Perception on Multirotors☆17Jun 24, 2026Updated 2 months ago
- Board: PYNQ-Z2, Vitis version: 2022.1☆20Sep 2, 2024Updated last year
- The official project website of "Small Scale Data-Free Knowledge Distillation" (SSD-KD for short, published in CVPR 2024).☆22Jun 13, 2024Updated 2 years ago
- Code for ICML 2023 paper "Quantifying the Knowledge in GNNs for Reliable Distillation into MLPs"☆22Sep 24, 2025Updated 11 months ago
- USB Type-C Power Delivery FPGA☆33Apr 24, 2026Updated 4 months ago
- ☆37Nov 11, 2018Updated 7 years ago
- 支持AXI总线协议的8k×8 SP SRAM☆28Mar 26, 2020Updated 6 years ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- Step by step tutorial for building CortexM0 SoC☆41Mar 29, 2022Updated 4 years ago
- Integrated Circuit Design Contest (ICDC) - 大學院校積體電路設計競賽☆25Apr 20, 2022Updated 4 years ago
- SDK for CeleX4 sensor.☆15Dec 12, 2019Updated 6 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆32Oct 30, 2015Updated 10 years ago
- SystemVerilog for Verification A Guide to Learning the Testbench Language Features Third Edition中文翻译☆22Jan 10, 2022Updated 4 years ago
- [ACM MM'24] CRLD: Cross-View Consistency Regularisation for Knowledge Distillation☆15Apr 10, 2025Updated last year
- ☆17Feb 9, 2023Updated 3 years ago