nqdtan / vck5000_vivado_ulpLinks
An alternative Vivado custom design example (to fully Vitis) for the User Logic Partition targeting VCK5000
☆13Updated last year
Alternatives and similar repositories for vck5000_vivado_ulp
Users that are interested in vck5000_vivado_ulp are comparing it to the libraries listed below
Sorting:
- Release of stream-specialization software/hardware stack.☆120Updated 2 years ago
- ☆61Updated 9 months ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆73Updated last year
- ☆26Updated 2 years ago
- ☆32Updated last year
- ☆108Updated last year
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆31Updated 4 years ago
- EQueue Dialect☆41Updated 3 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- Artifact evaluation of PLDI'24 paper "Allo: A Programming Model for Composable Accelerator Design"☆32Updated last year
- The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow☆46Updated 2 years ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆64Updated last year
- ☆29Updated 4 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 4 years ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆85Updated 2 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆73Updated 3 weeks ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆82Updated 6 years ago
- ☆13Updated 2 years ago
- ☆28Updated 2 years ago
- Processing in Memory Emulation☆22Updated 2 years ago
- PIMeval simulator and PIMbench suite☆42Updated last month
- MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator☆55Updated 4 years ago
- An Open-Source Tool for CGRA Accelerators☆81Updated 4 months ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆70Updated 3 months ago
- Benchmarks for Accelerator Design and Customized Architectures☆135Updated 5 years ago
- ☆10Updated 2 years ago
- An integrated CGRA design framework☆91Updated 9 months ago
- agile hardware-software co-design☆52Updated 4 years ago
- ☆70Updated 4 years ago