OpenTestability is an open-source tool for structural analysis of digital circuits, enabling computation of SCOAP metrics, Controllibility Observability Probability (COP), reconvergent path detection, and test point insertion.
☆20Aug 6, 2026Updated this week
Alternatives and similar repositories for OpenTestability
Users that are interested in OpenTestability are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Static timing analysis (STA) is a method of validating the timing performance of a design by checking all possible paths for timing viola…☆19Oct 4, 2022Updated 3 years ago
- A neural network fast inference library implementing Coral Edge TPU emulator using AVX2.☆15Mar 30, 2022Updated 4 years ago
- The purpose of the repo is to support CORE-V Wally architectural verification☆20Nov 11, 2025Updated 9 months ago
- Consolidated repository for course materials from the BEE program at NUST-SEECS☆21Apr 8, 2026Updated 4 months ago
- use Zybo z7-20☆17May 21, 2025Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ai_accelerator_basic_for_student (no solve)☆18Mar 27, 2020Updated 6 years ago
- RTLMeter benchmark suite☆31Jul 21, 2026Updated 2 weeks ago
- This is the repository containing the implementation of sparse dense matrix multiplication for the matrix dimension of 560 x 560.☆10Jul 7, 2021Updated 5 years ago
- Petri Net Simulator program☆10Nov 27, 2017Updated 8 years ago
- SPARX: An Open-Source, Automated, Programmatically Generated, Frequency-Scalable Six-Port Receiver in 130-nm CMOS☆30Jul 31, 2026Updated last week
- VHDL code generator for AXI4-lite register files☆13May 22, 2024Updated 2 years ago
- Open-source RTL logic simulator with GPU acceleration (Metal, CUDA, HIP/AMD)☆82Updated this week
- Working 8x8 systolic array hardware implemented in Xilinx Vivado, operated and controlled in software using Xilinx Vitis☆26Feb 16, 2024Updated 2 years ago
- Simodense: a RISC-V softcore for custom SIMD instructions☆17Updated this week
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- This repository presents the mixed signal design of a Counter Type/ Ramp Type ADC. The Digital part of the circuit i.e 4- bit counter is …☆12May 2, 2022Updated 4 years ago
- Hand Writing Digital Recognization Based on FPGA, we desiged a SoC embeded a Cortex M3 core and other peripherals，this SoC run a CNN. The…☆14Mar 30, 2023Updated 3 years ago
- Porting FreeRTOS to a RISC-V based system on PYNQ-Z2☆12Dec 26, 2024Updated last year
- Modular RISC-V implementation & SoC☆17Aug 3, 2026Updated last week
- Matrix multiplication accelerator on ZYNQ SoC.☆13Apr 29, 2025Updated last year
- High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model☆34Feb 2, 2026Updated 6 months ago
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆13Aug 26, 2023Updated 2 years ago
- SystemVerilog RTL Linter for YoSys☆24Nov 22, 2024Updated last year
- Fabric generator and CAD tools graphical frontend☆18Aug 5, 2025Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- RTL implementation of a ray-tracing GPU☆16Dec 18, 2012Updated 13 years ago
- Our contribution to the AMD Open Hardware Contest: A ML-based Deep Packet Inspection for RDMA-networking on FPGAs☆13May 6, 2026Updated 3 months ago
- LSTM neural network (verilog)☆16Dec 5, 2018Updated 7 years ago
- Research enablement kit for designing and prototyping a Cortex-M0–based SoC with custom IP integration (education, research)☆18Jun 13, 2025Updated last year
- This repo is to inplemente the riscv soc on the xilinx pynq-z2 board☆12Dec 6, 2023Updated 2 years ago
- Design files and associated documentation for Sonata PCB, part of the Sunburst Project☆22Apr 1, 2025Updated last year
- SystemVerilog file list pruner☆18Aug 2, 2026Updated last week
- Linter for SystemVerilog Assertions (SVA). Following the philosophy of BYOL - Build Your Own Linter, SVALint is an example of ho users ca…☆21Sep 10, 2025Updated 11 months ago
- RISC-V soft-SoC extensible plaftorm for Xilinx FPGAs from University of Naples Federico II.☆18Apr 26, 2026Updated 3 months ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Latest PyTorch Implementation of DeltaGRU & DeltaLSTM that Exploits Temporal Sparsity in Sequential Data☆18Sep 30, 2023Updated 2 years ago
- Administrative repository for the Attached Matrix Facility Task Group☆14Dec 11, 2023Updated 2 years ago
- Open-source implementations of reference Physical True Random Number Generators (TRNG or PTRNG) based on ring oscillators.☆19Mar 26, 2026Updated 4 months ago
- ☆17Jul 28, 2026Updated last week
- C++ framework for easier interaction with OpenGL code☆20Mar 24, 2013Updated 13 years ago
- FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters☆16May 26, 2021Updated 5 years ago
- Foundations for common LLM problems☆36May 29, 2026Updated 2 months ago