fcapz: Open-source, vendor-agnostic full-featured FPGA debug cores. Embedded Logic analyzer, Embedded I/O and Embedded JTAG-AXI
☆124Oct 2, 2026Updated this week
Alternatives and similar repositories for fpgacapZero
Users that are interested in fpgacapZero are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A flexible and scalable development platform for modern FPGA projects.☆47Sep 24, 2026Updated last week
- An open-source HDL register code generator fast enough to run in real time.☆91Sep 24, 2026Updated last week
- Open Logic FPGA Standard Library☆1,020Updated this week
- Example project for the BRS-100-GW1NR9 FPGA development board.☆19Sep 9, 2026Updated 3 weeks ago
- High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model☆35Feb 2, 2026Updated 8 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- The first-ever opensource soft core for PCIE EndPoint. Without vendor-locked HMs for Data Link, Transaction, Application layers. With sta…☆93Updated this week
- A Formal Verification Methodology to lower the adoption barriers for Formal Verification of ASIC and FPGA designs in the Space sector (th…☆25Jun 29, 2026Updated 3 months ago
- pcie datalink layer implementation in verilog/systemverilog☆18Sep 10, 2026Updated 3 weeks ago
- A collection of reusable, high-quality, peer-reviewed VHDL building blocks.☆219Sep 24, 2026Updated last week
- LiteX development baseboards arround the SQRL Acorn.☆78Updated this week
- ☆12Jun 4, 2021Updated 5 years ago
- LimeSDR XTRX gateware project.☆23Sep 3, 2026Updated last month
- Open-source SystemVerilog simulator in Rust. 4-state, event-driven, IEEE 1800-2023, runs real UVM.☆90Updated this week
- LiteX-based gateware for LimeSDR boards.☆22Updated this week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Experimental Lattice ECP5-driven Data Center Security Communication Module☆22Jul 22, 2024Updated 2 years ago
- Open-source RTL logic simulator with GPU acceleration (Metal, CUDA, HIP/AMD)☆87Aug 10, 2026Updated last month
- Interface definitions for VHDL-2019.☆36May 13, 2026Updated 4 months ago
- ☆16Apr 21, 2022Updated 4 years ago
- PCIe stack written in Amaranth.☆18Apr 27, 2026Updated 5 months ago
- The open-source Zynq 7000 BSP generator for openXC7☆64Jan 21, 2025Updated last year
- A curated list of awesome resources for HDL design and verification☆178Updated this week
- Limited python / cocotb interface to Xilinx/AMD Vivado simulator.☆76Updated this week
- Greyhound on IHP SG13G2 0.13 μm BiCMOS process☆110Aug 31, 2026Updated last month
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A huge VHDL library for FPGA and digital ASIC development☆478Updated this week
- This is an OOT module for GNU Radio integrating verilog simulation feature☆38Sep 23, 2019Updated 7 years ago
- Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments, allowing host compiled programs to run in a log…☆79Feb 12, 2026Updated 7 months ago
- WAL enables programmable waveform analysis.☆185Sep 22, 2026Updated last week
- A robust, open-source physical layer implementation for FPGA-to-FPGA communication over high-speed serial links of the Quantum Error Corr…☆36Sep 8, 2026Updated 3 weeks ago
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆38Feb 23, 2025Updated last year
- A configurable and approachable tool for FPGA debugging and rapid prototyping.☆151Aug 26, 2026Updated last month
- A Python package to use FPGA development tools programmatically.☆151Sep 21, 2026Updated last week
- Digital systems are clocked. This project is about constructing a high-Q clock by simmering an ordinary quartz crystal in a heavy numeric…☆24Sep 20, 2026Updated last week
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Experimental FPGA project for streaming two MIPI CSI camera streams to an HDMI monitor using a ULX3S FPGA board☆34May 15, 2023Updated 3 years ago
- Hardware design project of the FIX and TCP/IP offload engines on FPGA, containing HDL codes and Python codes for testing.☆25Dec 11, 2023Updated 2 years ago
- Opensource DDR3 Controller☆484Sep 12, 2026Updated 3 weeks ago
- FuseSoc Verification Automation☆22Jul 21, 2022Updated 4 years ago
- Interfacing VHDL and foreign languages with VUnit☆15Feb 20, 2020Updated 6 years ago
- BYU Pynq PR Video Pipeline Hardware☆12Oct 2, 2025Updated last year
- An open-source, JEDEC JESD270-4A-compliant HBM4 memory subsystem (controller + PHY-shim + DFT + RAS + security wrapper) tightly coupled t…☆27Jun 14, 2026Updated 3 months ago