chili-chips-ba / openCologne-PCIELinks
The first-ever opensource RTL core for PCIE EndPoint. Without vendor-locked HMs for Data Link, Transaction, Application layers; With standard PIPE interface for vendor SerDes. Portable, unencrypted, free SVerilog with best-in-class VIP, Slot and M.2 cards for GateMate, the project opens PCIE connectivity to FPGAs, ASICs, I/O, acceleration, AI, .…
☆30Updated last week
Alternatives and similar repositories for openCologne-PCIE
Users that are interested in openCologne-PCIE are comparing it to the libraries listed below
Sorting:
- USB virtual model in C++ for Verilog☆32Updated last year
- LunaPnR is a place and router for integrated circuits☆47Updated 3 months ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆37Updated last week
- Examples and design pattern for VHDL verification☆15Updated 9 years ago
- Library of reusable VHDL components☆28Updated last year
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆30Updated 3 years ago
- ☆26Updated 6 months ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆45Updated this week
- Convert an image to a GDS format for inclusion in a zerotoasic project☆15Updated 3 years ago
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆22Updated 2 years ago
- A padring generator for ASICs☆25Updated 2 years ago
- cryptography ip-cores in vhdl / verilog☆41Updated 4 years ago
- Virtual development board for HDL design☆42Updated 2 years ago
- UART cocotb module☆11Updated 4 years ago
- VHDL Code for infrastructural blocks (designed for FPGA)☆15Updated 2 years ago
- VHDL String Formatting Library☆25Updated last year
- SpiceBind – spice inside HDL simulator☆56Updated 3 months ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆55Updated last month
- CologneChip GateMate FPGA Module: GMM-7550☆24Updated last week
- cocotb extension for nMigen☆17Updated 3 years ago
- Project Peppercorn - GateMate FPGA Bitstream Documentation☆27Updated last week
- Generate symbols from HDL components/modules☆21Updated 2 years ago
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆33Updated 8 months ago
- VHDLproc is a VHDL preprocessor☆24Updated 3 years ago
- This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI work…☆10Updated 3 years ago
- Interfacing VHDL and foreign languages with VUnit☆15Updated 5 years ago
- Specification of the Wishbone SoC Interconnect Architecture☆47Updated 3 years ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆52Updated 2 years ago
- USB 2.0 Device IP core using Migen with out-of-box AXI Slave Interface☆12Updated 8 years ago
- Fixed-point math library with VHDL, Python and MATLAB support☆28Updated last week