The first-ever opensource soft core for PCIE EndPoint. Without vendor-locked HMs for Data Link, Transaction, Application layers. With standard PIPE interface for vendor SerDes. Portable, unencrypted, free SVerilog RTL with best-in-class VIP, M.2 and Edge cards for GateMate. Project opens PCIE connectivity to FPGAs, ASICs, I/O, acceleration, AI..…
☆100Oct 17, 2026Updated this week
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