mcjtag / bitonic_sorter
Bitonic sorter (Batcher's sorting network) written in Verilog.
☆29Updated 3 months ago
Alternatives and similar repositories for bitonic_sorter:
Users that are interested in bitonic_sorter are comparing it to the libraries listed below
- ☆24Updated 5 years ago
- ☆25Updated 4 years ago
- ☆27Updated 5 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆49Updated this week
- General Purpose AXI Direct Memory Access☆48Updated 8 months ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆33Updated 2 years ago
- ☆38Updated 2 years ago
- HLS for Networks-on-Chip☆33Updated 3 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆57Updated last year
- RTL code of some arbitration algorithm☆13Updated 5 years ago
- ☆40Updated 5 years ago
- SystemVerilog modules and classes commonly used for verification☆45Updated 3 weeks ago
- tpu-systolic-array-weight-stationary☆20Updated 3 years ago
- The memory model was leveraged from micron.☆22Updated 6 years ago
- Xilinx AXI VIP example of use☆33Updated 3 years ago
- Synopsys Design compiler, VCS and Tetra-MAX☆17Updated 6 years ago
- Development of a Network on Chip Simulation using SystemC.☆31Updated 7 years ago
- SoC Based on ARM Cortex-M3☆26Updated 2 weeks ago
- ☆50Updated 3 years ago
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables…☆30Updated 4 years ago
- 自建 chisel 工程模板☆12Updated last year
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆59Updated 5 years ago
- Base on Synopsys platform using VCS,DC,ICC,PT.☆11Updated 3 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆30Updated 6 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆27Updated 2 years ago
- CNN accelerator using NoC architecture☆15Updated 6 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆31Updated 2 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆47Updated 3 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆45Updated 4 years ago