Bitonic sorter (Batcher's sorting network) written in Verilog.
☆40Oct 4, 2024Updated 2 years ago
Alternatives and similar repositories for bitonic_sorter
Users that are interested in bitonic_sorter are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Implement a bitonic sorting network on FPGA☆50Nov 6, 2021Updated 4 years ago
- The Design and Implementation of a Pulse Compression Filter on an FPGA.☆37Aug 7, 2021Updated 5 years ago
- Wallace and Dadda tree multiplier generator in vhdl and verilog☆14Mar 14, 2026Updated 7 months ago
- This is a circular buffer controller used in FPGA.☆36Jan 12, 2016Updated 10 years ago
- Simple demo showing how to use the ping pong FIFO☆17May 2, 2016Updated 10 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Memory Controller IP Core☆10Jul 17, 2014Updated 12 years ago
- [DATE'23] The official code for paper <CLAP: Locality Aware and Parallel Triangle Counting with Content Addressable Memory>☆25Updated this week
- ☆15Apr 24, 2023Updated 3 years ago
- Repository for RTL building blocks #100daysofrtl VERILOG VHDL System Verilog☆14Jun 3, 2024Updated 2 years ago
- USB Full-Speed/Hi-Speed Device Controller core for FPGA☆34Nov 23, 2020Updated 5 years ago
- ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)☆13Aug 29, 2018Updated 8 years ago
- Build an open source, extremely simple DMA.☆25Feb 17, 2019Updated 7 years ago
- Xilinx IP repository☆13May 5, 2018Updated 8 years ago
- Simple and effective parallel CRC calculator written in synthesizable SystemVerilog☆15Apr 11, 2019Updated 7 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆13Dec 17, 2024Updated last year
- Example FPGA programs written using LegUp HLS☆11May 13, 2021Updated 5 years ago
- MT29F128G based NAND flash controller☆10Jun 17, 2021Updated 5 years ago
- 位宽和深度可定制的异步FIFO☆14May 29, 2024Updated 2 years ago
- An Open Source Link Protocol and Controller☆29Aug 1, 2021Updated 5 years ago
- 本工具用于自动生成一个Wallace Tree算法VerilogHDL代码实例，并附带了一些配套的工具和一个完整的VerilogHDL描述的乘法器。☆27Jun 1, 2023Updated 3 years ago
- This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI work…☆10Jan 13, 2022Updated 4 years ago
- ☆15Jul 28, 2022Updated 4 years ago
- 通过SPI协议实现FPGA multiboot在线升级功能☆13May 17, 2018Updated 8 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- The implementation of AD9371 on KC705☆21Jun 10, 2025Updated last year
- mirror of https://git.elphel.com/Elphel/x393☆40Mar 16, 2023Updated 3 years ago
- Here are some implementations of basic hardware units in RTL language (verilog for now), which can be used for area/power evaluation and …☆15Aug 25, 2023Updated 3 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆32Apr 25, 2016Updated 10 years ago
- Data Analysis on Weather Dataset using Python☆12Aug 15, 2024Updated 2 years ago
- Verilog Forward Error Correction Archive: BOX-Muller for fast AWGN generation, Universal Demapper from BPSK to QAM-512, different Forward…☆84Apr 28, 2023Updated 3 years ago
- Verification Template Engine is a Jinja2-based template engine targeted at verification engineers☆14Aug 31, 2026Updated last month
- Generate a Verilog Source file and testbench file for a given Moore FSM☆17Nov 18, 2012Updated 13 years ago
- DMA controller for CNN accelerator☆15May 22, 2017Updated 9 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- this repository is a project about iic master, created by gyj in second half of 2017☆18Jun 30, 2018Updated 8 years ago
- 2-core MIPS R10K OoO Processor with Snooping MSI and Pipeline Bus☆14Jan 5, 2018Updated 8 years ago
- An open source, parameterized SystemVerilog digital hardware IP library☆33May 26, 2024Updated 2 years ago
- Open Source SSD Controller. NVMe and Lightstor variants☆18May 21, 2014Updated 12 years ago
- Design a median filter for a Generic RGB image.☆14Mar 6, 2019Updated 7 years ago
- ☆37Jun 19, 2023Updated 3 years ago
- commit rtl and build cosim env☆16Feb 15, 2024Updated 2 years ago