mcjtag / bitonic_sorterLinks
Bitonic sorter (Batcher's sorting network) written in Verilog.
☆34Updated 10 months ago
Alternatives and similar repositories for bitonic_sorter
Users that are interested in bitonic_sorter are comparing it to the libraries listed below
Sorting:
- ☆34Updated 6 years ago
- ☆27Updated 5 years ago
- ☆60Updated 2 years ago
- HLS for Networks-on-Chip☆35Updated 4 years ago
- General Purpose AXI Direct Memory Access☆57Updated last year
- ☆29Updated 5 years ago
- 本工具用于自动生成一个Wallace Tree算法VerilogHDL代码实例,并附带了一些配套的工具和一个完整的VerilogHDL描述的乘法器。☆26Updated 2 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆56Updated 10 months ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆13Updated 2 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆67Updated 5 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated last week
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆41Updated 2 years ago
- Xilinx AXI VIP example of use☆42Updated 4 years ago
- A verilog implementation for Network-on-Chip☆76Updated 7 years ago
- SoC Based on ARM Cortex-M3☆32Updated 3 months ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- RTL code of some arbitration algorithm☆14Updated 6 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆19Updated 7 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Updated 4 years ago
- ☆53Updated 6 years ago
- Template for project1 TPU☆19Updated 4 years ago
- Open IP in Hardware Description Language.☆24Updated last year
- 128KB AXI cache (32-bit in, 256-bit out)☆53Updated 4 years ago
- ☆20Updated 2 years ago
- Verilog Implementation of 32-bit Floating Point Adder☆40Updated 5 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆66Updated last year
- 自建 chisel 工程模板☆14Updated 2 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆13Updated 3 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆29Updated 2 years ago