Bitonic sorter (Batcher's sorting network) written in Verilog.
☆40Oct 4, 2024Updated last year
Alternatives and similar repositories for bitonic_sorter
Users that are interested in bitonic_sorter are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Implement a bitonic sorting network on FPGA☆48Nov 6, 2021Updated 4 years ago
- The Design and Implementation of a Pulse Compression Filter on an FPGA.☆34Aug 7, 2021Updated 4 years ago
- Wallace and Dadda tree multiplier generator in vhdl and verilog☆13Mar 14, 2026Updated last month
- ☆14Jul 28, 2022Updated 3 years ago
- This is a circular buffer controller used in FPGA.☆35Jan 12, 2016Updated 10 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Simple demo showing how to use the ping pong FIFO☆16May 2, 2016Updated 9 years ago
- [DATE'23] The official code for paper <CLAP: Locality Aware and Parallel Triangle Counting with Content Addressable Memory>☆24Mar 16, 2026Updated last month
- ☆15Apr 24, 2023Updated 2 years ago
- USB Full-Speed/Hi-Speed Device Controller core for FPGA☆34Nov 23, 2020Updated 5 years ago
- ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)☆13Aug 29, 2018Updated 7 years ago
- Xilinx IP repository☆13May 5, 2018Updated 7 years ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆119Mar 24, 2026Updated 3 weeks ago
- Here are some implementations of basic hardware units in RTL language (verilog for now), which can be used for area/power evaluation and …☆14Aug 25, 2023Updated 2 years ago
- 位宽和深度可定制的异步FIFO☆14May 29, 2024Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- 通过SPI协议实现FPGA multiboot在线升级功能☆13May 17, 2018Updated 7 years ago
- This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI work…☆10Jan 13, 2022Updated 4 years ago
- Tutorials on Vitis AI Created by LogicTronix!☆35Jul 5, 2024Updated last year
- HDL and C source for WAVE Zynq Ultrascale+ SoC☆19Nov 16, 2021Updated 4 years ago
- 本工具用于自动生成一个Wallace Tree算法VerilogHDL代码实例，并附 带了一些配套的工具和一个完整的VerilogHDL描述的乘法器。☆27Jun 1, 2023Updated 2 years ago
- 2-core MIPS R10K OoO Processor with Snooping MSI and Pipeline Bus☆11Jan 5, 2018Updated 8 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆32Apr 25, 2016Updated 9 years ago
- The implementation of AD9371 on KC705☆20Jun 10, 2025Updated 10 months ago
- Verilog Forward Error Correction Archive: BOX-Muller for fast AWGN generation, Universal Demapper from BPSK to QAM-512, different Forward…☆81Apr 28, 2023Updated 2 years ago
- Wordpress hosting with auto-scaling - Free Trial • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- this repository is a project about iic master, created by gyj in second half of 2017☆18Jun 30, 2018Updated 7 years ago
- Generate a Verilog Source file and testbench file for a given Moore FSM☆17Nov 18, 2012Updated 13 years ago
- Verification Template Engine is a Jinja2-based template engine targeted at verification engineers☆14Jan 4, 2024Updated 2 years ago
- ☆37Jun 19, 2023Updated 2 years ago
- The official implementation of HPCA 2025 paper, Prosperity: Accelerating Spiking Neural Networks via Product Sparsity☆38Aug 9, 2025Updated 8 months ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆15Jan 22, 2025Updated last year
- commit rtl and build cosim env☆15Feb 15, 2024Updated 2 years ago
- USB capture IP☆25Jun 6, 2020Updated 5 years ago
- Ultra High Performance AXI4-based Direct Memory Access (DMA) Controller. This project was an interview assignment. Work in Progress.☆15Oct 19, 2024Updated last year
- Wordpress hosting with auto-scaling - Free Trial • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Simple and effective parallel CRC calculator written in synthesizable SystemVerilog☆15Apr 11, 2019Updated 7 years ago
- OpenExSys_NoC a mesh-based network on chip IP.☆20Dec 1, 2023Updated 2 years ago
- DMA controller for CNN accelerator☆14May 22, 2017Updated 8 years ago
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆55Aug 14, 2024Updated last year
- Groundhog - Serial ATA Host Bus Adapter☆23Jun 10, 2018Updated 7 years ago
- zynqmp_cam_isp_demo linux软件项目☆23Dec 18, 2022Updated 3 years ago
- VHDL Bypass descriptor controller for Xilinx DMA IP for PCIe☆18Oct 23, 2019Updated 6 years ago