amaranth-lang / rfcs

Related projects: ⓘ

• amaranth-lang / amaranth-stdio
  Industry standard I/O for Amaranth HDL
  ☆25Updated 2 months ago
• amaranth-lang / amaranth-soc
  System on Chip toolkit for Amaranth HDL
  ☆75Updated 2 weeks ago
• greatscottgadgets / bucatini
  a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface
  ☆31Updated 2 years ago
• amaranth-lang / amaranth-yosys
  WebAssembly-based Yosys distribution for Amaranth HDL
  ☆25Updated 3 weeks ago
• clairexen / picorv
  PicoRV
  ☆43Updated 4 years ago
• tomverbeure / cxxrtl_eval
  Experiments with Yosys cxxrtl backend
  ☆46Updated 8 months ago
• RobertBaruch / amaranth-tutorial
  ☆34Updated last year
• YosysHQ / prjtrellis-db
  Project Trellis database
  ☆12Updated 11 months ago
• GuzTech / misato
  RISC-V Processor written in Amaranth HDL
  ☆31Updated 2 years ago
• RobertBaruch / amaranth-exercises
  ☆22Updated last month
• m-labs / nmigen-soc
  System on Chip toolkit for nMigen
  ☆19Updated 4 years ago
• apertus-open-source-cinema / naps
  An experiment for building gateware for the axiom micro / beta using amaranth-hdl
  ☆37Updated 4 months ago
• sparrowgrine / prjtritium
  ☆22Updated 2 years ago
• jeanthom / gram
  DDR3 controller for nMigen (WIP)
  ☆14Updated 8 months ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆53Updated this week
• Ravenslofty / yosys-cookbook
  User-friendly explanation of Yosys options
  ☆111Updated 2 years ago
• m-labs / microscope
  Finding the bacteria in rotting FPGA designs.
  ☆13Updated 3 years ago
• gatecat / hrt
  Hot Reconfiguration Technology demo
  ☆38Updated 2 years ago
• fallen / SucreLA
  Open source Logic Analyzer based on LiteX SoC
  ☆24Updated 5 months ago
• mattvenn / magic-inverter
  an inverter drawn in magic with makefile to simulate
  ☆26Updated 2 years ago
• ECP5-PCIe / ECP5-PCIe
  Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe
  ☆92Updated last year
• rqou / KinglerPAR
  Next-Generation FPGA Place-and-Route
  ☆10Updated 6 years ago
• trabucayre / quickfeather-notes
  Notes, scripts and apps to quickfeather board
  ☆10Updated 2 years ago
• bieganski / mtkcpu
  RISC-V CPU implementation in Amaranth HDL (aka nMigen)
  ☆25Updated 3 weeks ago
• adamgreig / daqnet
  ☆63Updated 4 years ago
• wyvernSemi / usbModel
  USB virtual model in C++ for Verilog
  ☆26Updated 2 weeks ago
• YoWASP / yosys
  Unofficial Yosys WebAssembly packages
  ☆65Updated last week
• lachlansneff / ligeia
  A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.
  ☆19Updated 2 years ago
• openXC7 / toolchain-nix
  Nix flake for openXC7
  ☆24Updated last week
• cr1901 / sentinel
  Another size-optimized RISC-V CPU for your consideration.
  ☆46Updated 2 weeks ago