Ravenslofty / yosys-cookbookLinks
User-friendly explanation of Yosys options
☆113Updated 3 years ago
Alternatives and similar repositories for yosys-cookbook
Users that are interested in yosys-cookbook are comparing it to the libraries listed below
Sorting:
- System on Chip toolkit for Amaranth HDL☆91Updated 8 months ago
- Documenting Lattice's 28nm FPGA parts☆143Updated last year
- Board definitions for Amaranth HDL☆117Updated 2 months ago
- Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe☆97Updated 2 years ago
- A single-wire bi-directional chip-to-chip interface for FPGAs☆123Updated 8 years ago
- Project X-Ray Database: XC7 Series☆69Updated 3 years ago
- PicoRV☆44Updated 5 years ago
- Naive Educational RISC V processor☆84Updated 2 weeks ago
- Experiments with Yosys cxxrtl backend☆49Updated 5 months ago
- Miscellaneous ULX3S examples (advanced)☆78Updated this week
- Experimental flows using nextpnr for Xilinx devices☆48Updated 2 weeks ago
- A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.☆19Updated 2 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆64Updated 3 weeks ago
- CoreScore☆156Updated 4 months ago
- assorted library of utility cores for amaranth HDL☆92Updated 9 months ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆94Updated last week
- Specification of the Wishbone SoC Interconnect Architecture☆45Updated 3 years ago
- The Critical Path - a rambly FPGA blog☆49Updated 4 years ago
- 妖刀夢渡☆59Updated 6 years ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆69Updated 3 years ago
- Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.☆78Updated 3 years ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆88Updated 6 years ago
- Nitro USB FPGA core☆85Updated last year
- Programmer for the Lattice ECP5 series, making use of FTDI based adaptors☆90Updated 7 months ago
- USB Serial on the TinyFPGA BX☆136Updated 4 years ago
- ☆79Updated last year
- Exploring gate level simulation☆58Updated last month
- ☆22Updated 3 years ago
- Generate Zynq configurations without using the vendor GUI☆30Updated last year
- Ultimate ECP5 development board☆109Updated 5 years ago