PyFPGA / pyfpgaLinks
A Python package to use FPGA development tools programmatically.
☆143Updated 10 months ago
Alternatives and similar repositories for pyfpga
Users that are interested in pyfpga are comparing it to the libraries listed below
Sorting:
- An open-source HDL register code generator fast enough to run in real time.☆82Updated this week
- A collection of reusable, high-quality, peer-reviewed VHDL building blocks.☆197Updated this week
- Drawio => VHDL and Verilog☆61Updated 2 years ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆115Updated this week
- Limited python / cocotb interface to Xilinx/AMD Vivado simulator.☆74Updated 4 months ago
- Verilog digital signal processing components☆169Updated 3 years ago
- Control and Status Register map generator for HDL projects☆130Updated 8 months ago
- Control and status register code generator toolchain☆172Updated 2 months ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆77Updated 6 months ago
- Python script to transform a VCD file to wavedrom format☆84Updated 3 years ago
- FuseSoC standard core library☆151Updated last month
- A flexible and scalable development platform for modern FPGA projects.☆39Updated this week
- Extensible FPGA control platform☆61Updated 2 years ago
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆147Updated 2 years ago
- FPGA and Digital ASIC Build System☆81Updated this week
- Temporary repo to gather information about the Kria KV260 board☆76Updated 4 years ago
- An abstract language model of VHDL written in Python.☆60Updated last week
- A series of CORDIC related projects☆121Updated last year
- Fabric generator and CAD tools.☆215Updated last week
- ☆118Updated 2 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆74Updated 3 years ago
- 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…☆119Updated 4 years ago
- VHDL-2008 Support Library☆58Updated 9 years ago
- Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.☆267Updated 3 years ago
- IP Core Library - Published and maintained by the Open Source VHDL Group☆52Updated last month
- Streaming based VHDL parser.☆84Updated last year
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆53Updated 2 years ago
- ☆26Updated 2 years ago
- Framework Open EDA Gui☆73Updated last year
- Open-source high performance AXI4-based HyperRAM memory controller☆82Updated 3 years ago