Alternatives and similar repositories for pcie_7x:

Users that are interested in pcie_7x are comparing it to the libraries listed below

• openXC7 / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆42Updated this week
• GuzTech / misato
  RISC-V Processor written in Amaranth HDL
  ☆37Updated 3 years ago
• cr1901 / sentinel
  Another size-optimized RISC-V CPU for your consideration.
  ☆58Updated 3 weeks ago
• Wren6991 / libfpga
  Reusable Verilog 2005 components for FPGA designs
  ☆42Updated 2 months ago
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆90Updated 7 months ago
• epsilon537 / boxlambda
  FPGA based microcomputer sandbox for software and RTL experimentation
  ☆54Updated this week
• sylefeb / Silixel
  Exploring gate level simulation
  ☆56Updated this week
• Ravenslofty / yosys-cookbook
  User-friendly explanation of Yosys options
  ☆112Updated 3 years ago
• apertus-open-source-cinema / naps
  An experiment for building gateware for the axiom micro / beta using amaranth-hdl
  ☆40Updated last week
• amaranth-lang / amaranth-soc
  System on Chip toolkit for Amaranth HDL
  ☆88Updated 6 months ago
• tomverbeure / cxxrtl_eval
  Experiments with Yosys cxxrtl backend
  ☆48Updated 3 months ago
• bieganski / mtkcpu
  RISC-V CPU implementation in Amaranth HDL (aka nMigen)
  ☆29Updated 7 months ago
• colognechip / gatemate_ila
  The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …
  ☆50Updated 3 months ago
• tomverbeure / gdbwave
  GDB server to debug CPU simulation waveform traces
  ☆44Updated 3 years ago
• craigjb / fuse-zynq
  Generate Zynq configurations without using the vendor GUI
  ☆30Updated last year
• f4pga / prjtrellis
  Documenting the Lattice ECP5 bit-stream format.
  ☆54Updated last year
• j-core / jcore-cpu
  J-Core J2/J32 5 stage pipeline CPU core
  ☆52Updated 4 years ago
• zephray / RISu064
  Dual-issue RV64IM processor for fun & learning
  ☆60Updated last year
• Featherweight-IP / fwrisc
  Featherweight RISC-V implementation
  ☆52Updated 3 years ago
• clairexen / picorv
  PicoRV
  ☆44Updated 5 years ago
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆89Updated 4 years ago
• emard / ulx3s-misc
  Miscellaneous ULX3S examples (advanced)
  ☆77Updated last month
• FPGAwars / FLIX-V
  FLIX-V: FPGA, Linux and RISC-V
  ☆41Updated last year
• openXC7 / toolchain-installer
  Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7
  ☆71Updated 10 months ago
• smunaut / iCE40linux
  Gateware / Firmware / BuildRoot to run linux on iCE40 / iCEBreaker
  ☆98Updated 2 years ago
• openXC7 / openXC7-snap
  snap package for nextpnr PnR FPGA toolchain for Xilinx 7 series FPGAs, with Spartan7, Artix7, Zynq7 and Kintex7 support
  ☆28Updated 9 months ago
• splinedrive / my_hdmi_device
  New clean hdmi implementation for ulx3s, icestick, icoboard, arty7, colorlight i5 and blackicemx! With tmds encoding hacked down from dvi…
  ☆96Updated last year
• prjunnamed / prjcombine
  An FPGA reverse engineering and documentation project
  ☆43Updated 2 weeks ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated last month
• tomverbeure / ecp5_jtag
  Use ECP5 JTAG port to interact with user design
  ☆26Updated 3 years ago